mirror of
https://github.com/openwrt/openwrt.git
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0efec6a008
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
lantiq/Easybox 904 xDSL
Run-tested: ipq806x/R7800, lantiq/Easybox 904 xDSL
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[add lantiq test reports]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
316 lines
8.1 KiB
Diff
316 lines
8.1 KiB
Diff
From 75f4d8d10e016f7428c268424483a927ee7a78bb Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@armlinux.org.uk>
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Date: Wed, 11 Dec 2019 10:56:56 +0000
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Subject: [PATCH] net: phy: add Broadcom BCM84881 PHY driver
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Add a rudimentary Clause 45 driver for the BCM84881 PHY, found on
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Methode DM7052 SFPs.
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/Kconfig | 6 +
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drivers/net/phy/Makefile | 1 +
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drivers/net/phy/bcm84881.c | 269 +++++++++++++++++++++++++++++++++++++
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3 files changed, 276 insertions(+)
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create mode 100644 drivers/net/phy/bcm84881.c
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -330,6 +330,12 @@ config BROADCOM_PHY
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Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
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BCM5481, BCM54810 and BCM5482 PHYs.
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+config BCM84881_PHY
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+ tristate "Broadcom BCM84881 PHY"
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+ depends on PHYLIB
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+ ---help---
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+ Support the Broadcom BCM84881 PHY.
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+
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config CICADA_PHY
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tristate "Cicada PHYs"
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---help---
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--- a/drivers/net/phy/Makefile
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+++ b/drivers/net/phy/Makefile
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@@ -62,6 +62,7 @@ obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o
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obj-$(CONFIG_BCM_CYGNUS_PHY) += bcm-cygnus.o
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obj-$(CONFIG_BCM_NET_PHYLIB) += bcm-phy-lib.o
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obj-$(CONFIG_BROADCOM_PHY) += broadcom.o
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+obj-$(CONFIG_BCM84881_PHY) += bcm84881.o
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obj-$(CONFIG_CICADA_PHY) += cicada.o
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obj-$(CONFIG_CORTINA_PHY) += cortina.o
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obj-$(CONFIG_DAVICOM_PHY) += davicom.o
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--- /dev/null
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+++ b/drivers/net/phy/bcm84881.c
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@@ -0,0 +1,269 @@
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+// SPDX-License-Identifier: GPL-2.0
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+// Broadcom BCM84881 NBASE-T PHY driver, as found on a SFP+ module.
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+// Copyright (C) 2019 Russell King, Deep Blue Solutions Ltd.
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+//
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+// Like the Marvell 88x3310, the Broadcom 84881 changes its host-side
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+// interface according to the operating speed between 10GBASE-R,
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+// 2500BASE-X and SGMII (but unlike the 88x3310, without the control
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+// word).
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+//
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+// This driver only supports those aspects of the PHY that I'm able to
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+// observe and test with the SFP+ module, which is an incomplete subset
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+// of what this PHY is able to support. For example, I only assume it
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+// supports a single lane Serdes connection, but it may be that the PHY
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+// is able to support more than that.
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+#include <linux/delay.h>
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+#include <linux/module.h>
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+#include <linux/phy.h>
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+
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+enum {
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+ MDIO_AN_C22 = 0xffe0,
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+};
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+
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+static int bcm84881_wait_init(struct phy_device *phydev)
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+{
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+ unsigned int tries = 20;
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+ int ret, val;
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+
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+ do {
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+ val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
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+ if (val < 0) {
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+ ret = val;
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+ break;
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+ }
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+ if (!(val & MDIO_CTRL1_RESET)) {
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+ ret = 0;
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+ break;
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+ }
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+ if (!--tries) {
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+ ret = -ETIMEDOUT;
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+ break;
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+ }
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+ msleep(100);
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+ } while (1);
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+
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+ if (ret)
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+ phydev_err(phydev, "%s failed: %d\n", __func__, ret);
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+
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+ return ret;
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+}
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+
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+static int bcm84881_config_init(struct phy_device *phydev)
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+{
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+ switch (phydev->interface) {
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+ case PHY_INTERFACE_MODE_SGMII:
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+ case PHY_INTERFACE_MODE_2500BASEX:
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+ case PHY_INTERFACE_MODE_10GKR:
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+ break;
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+ default:
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+ return -ENODEV;
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+ }
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+ return 0;
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+}
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+
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+static int bcm84881_probe(struct phy_device *phydev)
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+{
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+ /* This driver requires PMAPMD and AN blocks */
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+ const u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
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+
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+ if (!phydev->is_c45 ||
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+ (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
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+ return -ENODEV;
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+
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+ return 0;
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+}
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+
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+static int bcm84881_get_features(struct phy_device *phydev)
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+{
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+ int ret;
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+
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+ ret = genphy_c45_pma_read_abilities(phydev);
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+ if (ret)
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+ return ret;
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+
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+ /* Although the PHY sets bit 1.11.8, it does not support 10M modes */
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+ linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
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+ phydev->supported);
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+ linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
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+ phydev->supported);
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+
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+ return 0;
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+}
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+
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+static int bcm84881_config_aneg(struct phy_device *phydev)
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+{
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+ bool changed = false;
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+ u32 adv;
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+ int ret;
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+
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+ /* Wait for the PHY to finish initialising, otherwise our
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+ * advertisement may be overwritten.
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+ */
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+ ret = bcm84881_wait_init(phydev);
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+ if (ret)
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+ return ret;
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+
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+ /* We don't support manual MDI control */
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+ phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
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+
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+ /* disabled autoneg doesn't seem to work with this PHY */
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+ if (phydev->autoneg == AUTONEG_DISABLE)
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+ return -EINVAL;
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+
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+ ret = genphy_c45_an_config_aneg(phydev);
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+ if (ret < 0)
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+ return ret;
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+ if (ret > 0)
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+ changed = true;
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+
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+ adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
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+ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
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+ MDIO_AN_C22 + MII_CTRL1000,
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+ ADVERTISE_1000FULL | ADVERTISE_1000HALF,
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+ adv);
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+ if (ret < 0)
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+ return ret;
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+ if (ret > 0)
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+ changed = true;
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+
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+ return genphy_c45_check_and_restart_aneg(phydev, changed);
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+}
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+
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+static int bcm84881_aneg_done(struct phy_device *phydev)
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+{
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+ int bmsr, val;
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+
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+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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+ if (val < 0)
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+ return val;
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+
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+ bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
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+ if (bmsr < 0)
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+ return val;
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+
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+ return !!(val & MDIO_AN_STAT1_COMPLETE) &&
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+ !!(bmsr & BMSR_ANEGCOMPLETE);
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+}
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+
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+static int bcm84881_read_status(struct phy_device *phydev)
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+{
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+ unsigned int mode;
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+ int bmsr, val;
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+
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+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
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+ if (val < 0)
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+ return val;
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+
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+ if (val & MDIO_AN_CTRL1_RESTART) {
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+ phydev->link = 0;
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+ return 0;
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+ }
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+
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+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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+ if (val < 0)
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+ return val;
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+
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+ bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
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+ if (bmsr < 0)
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+ return val;
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+
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+ phydev->autoneg_complete = !!(val & MDIO_AN_STAT1_COMPLETE) &&
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+ !!(bmsr & BMSR_ANEGCOMPLETE);
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+ phydev->link = !!(val & MDIO_STAT1_LSTATUS) &&
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+ !!(bmsr & BMSR_LSTATUS);
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+ if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete)
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+ phydev->link = false;
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+
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+ if (!phydev->link)
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+ return 0;
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+
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+ linkmode_zero(phydev->lp_advertising);
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+ phydev->speed = SPEED_UNKNOWN;
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+ phydev->duplex = DUPLEX_UNKNOWN;
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+ phydev->pause = 0;
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+ phydev->asym_pause = 0;
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+ phydev->mdix = 0;
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+
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+ if (phydev->autoneg_complete) {
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+ val = genphy_c45_read_lpa(phydev);
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+ if (val < 0)
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+ return val;
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+
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+ val = phy_read_mmd(phydev, MDIO_MMD_AN,
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+ MDIO_AN_C22 + MII_STAT1000);
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+ if (val < 0)
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+ return val;
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+
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+ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
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+
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+ if (phydev->autoneg == AUTONEG_ENABLE)
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+ phy_resolve_aneg_linkmode(phydev);
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+ }
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+
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+ if (phydev->autoneg == AUTONEG_DISABLE) {
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+ /* disabled autoneg doesn't seem to work, so force the link
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+ * down.
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+ */
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+ phydev->link = 0;
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+ return 0;
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+ }
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+
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+ /* Set the host link mode - we set the phy interface mode and
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+ * the speed according to this register so that downshift works.
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+ * We leave the duplex setting as per the resolution from the
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+ * above.
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+ */
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+ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011);
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+ mode = (val & 0x1e) >> 1;
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+ if (mode == 1 || mode == 2)
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+ phydev->interface = PHY_INTERFACE_MODE_SGMII;
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+ else if (mode == 3)
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+ phydev->interface = PHY_INTERFACE_MODE_10GKR;
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+ else if (mode == 4)
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+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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+ switch (mode & 7) {
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+ case 1:
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+ phydev->speed = SPEED_100;
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+ break;
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+ case 2:
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+ phydev->speed = SPEED_1000;
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+ break;
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+ case 3:
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+ phydev->speed = SPEED_10000;
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+ break;
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+ case 4:
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+ phydev->speed = SPEED_2500;
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+ break;
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+ case 5:
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+ phydev->speed = SPEED_5000;
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+ break;
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+ }
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+
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+ return genphy_c45_read_mdix(phydev);
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+}
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+
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+static struct phy_driver bcm84881_drivers[] = {
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+ {
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+ .phy_id = 0xae025150,
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+ .phy_id_mask = 0xfffffff0,
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+ .name = "Broadcom BCM84881",
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+ .config_init = bcm84881_config_init,
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+ .probe = bcm84881_probe,
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+ .get_features = bcm84881_get_features,
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+ .config_aneg = bcm84881_config_aneg,
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+ .aneg_done = bcm84881_aneg_done,
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+ .read_status = bcm84881_read_status,
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+ },
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+};
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+
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+module_phy_driver(bcm84881_drivers);
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+
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+/* FIXME: module auto-loading for Clause 45 PHYs seems non-functional */
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+static struct mdio_device_id __maybe_unused bcm84881_tbl[] = {
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+ { 0xae025150, 0xfffffff0 },
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+ { },
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+};
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+MODULE_AUTHOR("Russell King");
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+MODULE_DESCRIPTION("Broadcom BCM84881 PHY driver");
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+MODULE_DEVICE_TABLE(mdio, bcm84881_tbl);
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+MODULE_LICENSE("GPL");
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