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6092c39c13
Backport in-SoC Gigabit Ethernet PHY driver instead of carrying the
driver in files-5.15.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 9fac590096)
214 lines
6.6 KiB
Diff
214 lines
6.6 KiB
Diff
From 5d2d78860f98eb5c03bc404eb024606878901ac8 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 13 Jun 2023 03:27:14 +0100
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Subject: [PATCH] net: phy: mediatek-ge-soc: initialize MT7988 PHY LEDs default
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state
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Initialize LEDs and set sane default values.
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Read boottrap register and apply LED polarities accordingly to get
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uniform behavior from all LEDs on MT7988.
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Requires syscon phandle 'mediatek,pio' present in parenting MDIO bus
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which should point to the syscon holding the boottrap register.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/phy/mediatek-ge-soc.c | 144 ++++++++++++++++++++++++++++--
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1 file changed, 136 insertions(+), 8 deletions(-)
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--- a/drivers/net/phy/mediatek-ge-soc.c
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+++ b/drivers/net/phy/mediatek-ge-soc.c
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@@ -1,11 +1,13 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <linux/bitfield.h>
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+#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/phy.h>
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+#include <linux/regmap.h>
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#define MTK_GPHY_ID_MT7981 0x03a29461
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#define MTK_GPHY_ID_MT7988 0x03a29481
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@@ -208,9 +210,40 @@
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#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
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#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
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+/* Registers on MDIO_MMD_VEND2 */
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+#define MTK_PHY_LED0_ON_CTRL 0x24
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+#define MTK_PHY_LED1_ON_CTRL 0x26
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+#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
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+#define MTK_PHY_LED_ON_LINK1000 BIT(0)
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+#define MTK_PHY_LED_ON_LINK100 BIT(1)
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+#define MTK_PHY_LED_ON_LINK10 BIT(2)
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+#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
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+#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
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+#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
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+#define MTK_PHY_LED_FORCE_ON BIT(6)
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+#define MTK_PHY_LED_POLARITY BIT(14)
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+#define MTK_PHY_LED_ENABLE BIT(15)
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+
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+#define MTK_PHY_LED0_BLINK_CTRL 0x25
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+#define MTK_PHY_LED1_BLINK_CTRL 0x27
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+#define MTK_PHY_LED_1000TX BIT(0)
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+#define MTK_PHY_LED_1000RX BIT(1)
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+#define MTK_PHY_LED_100TX BIT(2)
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+#define MTK_PHY_LED_100RX BIT(3)
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+#define MTK_PHY_LED_10TX BIT(4)
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+#define MTK_PHY_LED_10RX BIT(5)
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+#define MTK_PHY_LED_COLLISION BIT(6)
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+#define MTK_PHY_LED_RX_CRC_ERR BIT(7)
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+#define MTK_PHY_LED_RX_IDLE_ERR BIT(8)
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+#define MTK_PHY_LED_FORCE_BLINK BIT(9)
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+
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#define MTK_PHY_RG_BG_RASEL 0x115
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#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
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+/* Register in boottrap syscon defining the initial state of the 4 PHY LEDs */
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+#define RG_GPIO_MISC_TPBANK0 0x6f0
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+#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)
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+
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/* These macro privides efuse parsing for internal phy. */
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#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
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#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
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@@ -238,13 +271,6 @@ enum {
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PAIR_D,
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};
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-enum {
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- GPHY_PORT0,
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- GPHY_PORT1,
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- GPHY_PORT2,
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- GPHY_PORT3,
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-};
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-
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enum calibration_mode {
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EFUSE_K,
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SW_K
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@@ -263,6 +289,10 @@ enum CAL_MODE {
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SW_M
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};
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+struct mtk_socphy_shared {
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+ u32 boottrap;
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+};
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+
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static int mtk_socphy_read_page(struct phy_device *phydev)
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{
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return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
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@@ -1073,6 +1103,104 @@ static int mt798x_phy_config_init(struct
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return mt798x_phy_calibration(phydev);
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}
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+static int mt798x_phy_setup_led(struct phy_device *phydev, bool inverted)
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+{
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+ struct pinctrl *pinctrl;
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+ const u16 led_on_ctrl_defaults = MTK_PHY_LED_ENABLE |
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+ MTK_PHY_LED_ON_LINK1000 |
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+ MTK_PHY_LED_ON_LINK100 |
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+ MTK_PHY_LED_ON_LINK10;
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+ const u16 led_blink_defaults = MTK_PHY_LED_1000TX |
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+ MTK_PHY_LED_1000RX |
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+ MTK_PHY_LED_100TX |
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+ MTK_PHY_LED_100RX |
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+ MTK_PHY_LED_10TX |
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+ MTK_PHY_LED_10RX;
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+
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+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
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+ led_on_ctrl_defaults ^
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+ (inverted ? MTK_PHY_LED_POLARITY : 0));
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+
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+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
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+ led_on_ctrl_defaults);
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+
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+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
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+ led_blink_defaults);
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+
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+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL,
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+ led_blink_defaults);
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+
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+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
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+ if (IS_ERR(pinctrl))
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+ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED\n");
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+
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+ return 0;
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+}
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+
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+static int mt7988_phy_probe_shared(struct phy_device *phydev)
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+{
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+ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
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+ struct mtk_socphy_shared *priv = phydev->shared->priv;
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+ struct regmap *regmap;
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+ u32 reg;
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+ int ret;
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+
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+ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
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+ * LED_C and LED_D respectively. At the same time those pins are used to
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+ * bootstrap configuration of the reference clock source (LED_A),
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+ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
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+ * In practise this is done using a LED and a resistor pulling the pin
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+ * either to GND or to VIO.
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+ * The detected value at boot time is accessible at run-time using the
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+ * TPBANK0 register located in the gpio base of the pinctrl, in order
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+ * to read it here it needs to be referenced by a phandle called
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+ * 'mediatek,pio' in the MDIO bus hosting the PHY.
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+ * The 4 bits in TPBANK0 are kept as package shared data and are used to
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+ * set LED polarity for each of the LED0.
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+ */
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+ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
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+ if (IS_ERR(regmap))
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+ return PTR_ERR(regmap);
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+
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+ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®);
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+ if (ret)
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+ return ret;
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+
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+ priv->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
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+
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+ return 0;
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+}
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+
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+static bool mt7988_phy_get_boottrap_polarity(struct phy_device *phydev)
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+{
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+ struct mtk_socphy_shared *priv = phydev->shared->priv;
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+
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+ if (priv->boottrap & BIT(phydev->mdio.addr))
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+ return false;
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+
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+ return true;
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+}
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+
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+static int mt7988_phy_probe(struct phy_device *phydev)
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+{
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+ int err;
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+
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+ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
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+ sizeof(struct mtk_socphy_shared));
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+ if (err)
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+ return err;
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+
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+ if (phy_package_probe_once(phydev)) {
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+ err = mt7988_phy_probe_shared(phydev);
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+ if (err)
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+ return err;
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+ }
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+
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+ mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev));
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+
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+ return mt798x_phy_calibration(phydev);
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+}
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+
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static struct phy_driver mtk_socphy_driver[] = {
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{
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PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
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@@ -1092,7 +1220,7 @@ static struct phy_driver mtk_socphy_driv
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.config_init = mt798x_phy_config_init,
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.config_intr = genphy_no_config_intr,
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.handle_interrupt = genphy_handle_interrupt_no_ack,
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- .probe = mt798x_phy_calibration,
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+ .probe = mt7988_phy_probe,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.read_page = mtk_socphy_read_page,
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