mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 10:08:59 +00:00
96392789ae
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.43 All patches automatically rebased. Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/16010 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
181 lines
4.0 KiB
Diff
181 lines
4.0 KiB
Diff
From 8f053e5616352943e16966f195f5a7a161e6fe7d Mon Sep 17 00:00:00 2001
|
|
From: Mantas Pucka <mantas@8devices.com>
|
|
Date: Thu, 25 Jan 2024 11:04:12 +0200
|
|
Subject: [PATCH] arm64: dts: qcom: ipq6018: add thermal zones
|
|
|
|
Add thermal zones to make use of thermal sensors data. For CPU zone,
|
|
add cooling device that uses CPU frequency scaling.
|
|
|
|
Signed-off-by: Mantas Pucka <mantas@8devices.com>
|
|
Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.com
|
|
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
---
|
|
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++
|
|
1 file changed, 121 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
|
|
@@ -9,6 +9,7 @@
|
|
#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
|
|
#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
|
|
#include <dt-bindings/clock/qcom,apss-ipq.h>
|
|
+#include <dt-bindings/thermal/thermal.h>
|
|
|
|
/ {
|
|
#address-cells = <2>;
|
|
@@ -43,6 +44,7 @@
|
|
clock-names = "cpu";
|
|
operating-points-v2 = <&cpu_opp_table>;
|
|
cpu-supply = <&ipq6018_s2>;
|
|
+ #cooling-cells = <2>;
|
|
};
|
|
|
|
CPU1: cpu@1 {
|
|
@@ -55,6 +57,7 @@
|
|
clock-names = "cpu";
|
|
operating-points-v2 = <&cpu_opp_table>;
|
|
cpu-supply = <&ipq6018_s2>;
|
|
+ #cooling-cells = <2>;
|
|
};
|
|
|
|
CPU2: cpu@2 {
|
|
@@ -67,6 +70,7 @@
|
|
clock-names = "cpu";
|
|
operating-points-v2 = <&cpu_opp_table>;
|
|
cpu-supply = <&ipq6018_s2>;
|
|
+ #cooling-cells = <2>;
|
|
};
|
|
|
|
CPU3: cpu@3 {
|
|
@@ -79,6 +83,7 @@
|
|
clock-names = "cpu";
|
|
operating-points-v2 = <&cpu_opp_table>;
|
|
cpu-supply = <&ipq6018_s2>;
|
|
+ #cooling-cells = <2>;
|
|
};
|
|
|
|
L2_0: l2-cache {
|
|
@@ -890,6 +895,122 @@
|
|
};
|
|
};
|
|
|
|
+ thermal-zones {
|
|
+ nss-top-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+ thermal-sensors = <&tsens 4>;
|
|
+
|
|
+ trips {
|
|
+ nss-top-critical {
|
|
+ temperature = <125000>;
|
|
+ hysteresis = <1000>;
|
|
+ type = "critical";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ nss-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+ thermal-sensors = <&tsens 5>;
|
|
+
|
|
+ trips {
|
|
+ nss-critical {
|
|
+ temperature = <125000>;
|
|
+ hysteresis = <1000>;
|
|
+ type = "critical";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wcss-phya0-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+ thermal-sensors = <&tsens 7>;
|
|
+
|
|
+ trips {
|
|
+ wcss-phya0-critical {
|
|
+ temperature = <125000>;
|
|
+ hysteresis = <1000>;
|
|
+ type = "critical";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wcss-phya1-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+ thermal-sensors = <&tsens 8>;
|
|
+
|
|
+ trips {
|
|
+ wcss-phya1-critical {
|
|
+ temperature = <125000>;
|
|
+ hysteresis = <1000>;
|
|
+ type = "critical";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cpu-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+ thermal-sensors = <&tsens 13>;
|
|
+
|
|
+ trips {
|
|
+ cpu-critical {
|
|
+ temperature = <125000>;
|
|
+ hysteresis = <1000>;
|
|
+ type = "critical";
|
|
+ };
|
|
+
|
|
+ cpu_alert: cpu-passive {
|
|
+ temperature = <110000>;
|
|
+ hysteresis = <1000>;
|
|
+ type = "passive";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cooling-maps {
|
|
+ map0 {
|
|
+ trip = <&cpu_alert>;
|
|
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ lpass-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+ thermal-sensors = <&tsens 14>;
|
|
+
|
|
+ trips {
|
|
+ lpass-critical {
|
|
+ temperature = <125000>;
|
|
+ hysteresis = <1000>;
|
|
+ type = "critical";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ddrss-top-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+ thermal-sensors = <&tsens 15>;
|
|
+
|
|
+ trips {
|
|
+ ddrss-top-critical {
|
|
+ temperature = <125000>;
|
|
+ hysteresis = <1000>;
|
|
+ type = "critical";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|