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51 lines
1.3 KiB
Diff
51 lines
1.3 KiB
Diff
From d3c1e72c755cf67427b5d410039a096520d6537f Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 7 Dec 2015 17:19:55 +0100
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Subject: [PATCH 18/53] arch: mips: ralink: reset pci prior to reboot
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/reset.c | 12 ++++++++++--
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1 file changed, 10 insertions(+), 2 deletions(-)
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diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
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index ee26d45..ee117c4 100644
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--- a/arch/mips/ralink/reset.c
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+++ b/arch/mips/ralink/reset.c
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@@ -11,6 +11,7 @@
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#include <linux/pm.h>
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#include <linux/io.h>
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#include <linux/of.h>
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+#include <linux/delay.h>
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#include <linux/reset-controller.h>
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#include <asm/reboot.h>
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@@ -18,8 +19,10 @@
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#include <asm/mach-ralink/ralink_regs.h>
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/* Reset Control */
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-#define SYSC_REG_RESET_CTRL 0x034
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-#define RSTCTL_RESET_SYSTEM BIT(0)
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+#define SYSC_REG_RESET_CTRL 0x034
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+
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+#define RSTCTL_RESET_PCI BIT(26)
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+#define RSTCTL_RESET_SYSTEM BIT(0)
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static int ralink_assert_device(struct reset_controller_dev *rcdev,
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unsigned long id)
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@@ -83,6 +86,11 @@ void ralink_rst_init(void)
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static void ralink_restart(char *command)
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{
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+ if (IS_ENABLED(CONFIG_PCI)) {
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+ rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
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+ mdelay(50);
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+ }
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+
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local_irq_disable();
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rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
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unreachable();
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--
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1.7.10.4
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