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This backports commits from master that fix AES ciphers when using the qce driver: - A couple of simple fixes for CTR and XTS modes used with AES: * 041-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch * 042-crypto-qce-fix-xts-aes-qce-key-sizes.patch - A fix for a bug that affected cases when there were more entries in the input sg list than necessary to actually encrypt, resulting in failure in gcm, where the authentication tag is present after the encryption data: * 043-crypto-qce-save-a-sg-table-slot-for-result-buf.patch - A fix to update the IV buffer passed to the driver from the kernel: * 044-crypto-qce-update-the-skcipher-IV.patch - A patch that reduces memory footprint and driver initialization by only initializing the fallback mechanism where it is actually used: * 046-crypto-qce-initialize-fallback-only-for-AES.patch - Three patches that make gcm and xts modes work with the qce driver, and improve performance with small blocks: * 047-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch * 048-crypto-qce-use-AES-fallback-for-small-requests.patch * 049-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch - A patch that allows the hashes/ciphers to be built individually. * 051-crypto-qce-allow-building-only-hashes-ciphers.patch Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com> [renumbered patches, added patches from dropped commit, refreshed, 5.4] Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
114 lines
4.3 KiB
Diff
114 lines
4.3 KiB
Diff
From ce163ba0bf298f1707321ac025ef639f88e62801 Mon Sep 17 00:00:00 2001
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From: Eneas U de Queiroz <cotequeiroz@gmail.com>
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Date: Fri, 7 Feb 2020 12:02:26 -0300
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Subject: [PATCH 10/11] crypto: qce - use AES fallback for small requests
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Process small blocks using the fallback cipher, as a workaround for an
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observed failure (DMA-related, apparently) when computing the GCM ghash
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key. This brings a speed gain as well, since it avoids the latency of
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using the hardware engine to process small blocks.
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Using software for all 16-byte requests would be enough to make GCM
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work, but to increase performance, a larger threshold would be better.
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Measuring the performance of supported ciphers with openssl speed,
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software matches hardware at around 768-1024 bytes.
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Considering the 256-bit ciphers, software is 2-3 times faster than qce
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at 256-bytes, 30% faster at 512, and about even at 768-bytes. With
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128-bit keys, the break-even point would be around 1024-bytes.
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This adds the 'aes_sw_max_len' parameter, to set the largest request
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length processed by the software fallback. Its default is being set to
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512 bytes, a little lower than the break-even point, to balance the cost
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in CPU usage.
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Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
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Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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---
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--- a/drivers/crypto/Kconfig
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+++ b/drivers/crypto/Kconfig
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@@ -628,6 +628,29 @@ config CRYPTO_DEV_QCE
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hardware. To compile this driver as a module, choose M here. The
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module will be called qcrypto.
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+config CRYPTO_DEV_QCE_SW_MAX_LEN
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+ int "Default maximum request size to use software for AES"
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+ depends on CRYPTO_DEV_QCE && CRYPTO_DEV_QCE_SKCIPHER
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+ default 512
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+ help
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+ This sets the default maximum request size to perform AES requests
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+ using software instead of the crypto engine. It can be changed by
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+ setting the aes_sw_max_len parameter.
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+
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+ Small blocks are processed faster in software than hardware.
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+ Considering the 256-bit ciphers, software is 2-3 times faster than
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+ qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
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+ With 128-bit keys, the break-even point would be around 1024-bytes.
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+
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+ The default is set a little lower, to 512 bytes, to balance the
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+ cost in CPU usage. The minimum recommended setting is 16-bytes
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+ (1 AES block), since AES-GCM will fail if you set it lower.
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+ Setting this to zero will send all requests to the hardware.
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+
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+ Note that 192-bit keys are not supported by the hardware and are
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+ always processed by the software fallback, and all DES requests
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+ are done by the hardware.
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+
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config CRYPTO_DEV_QCOM_RNG
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tristate "Qualcomm Random Number Generator Driver"
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depends on ARCH_QCOM || COMPILE_TEST
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--- a/drivers/crypto/qce/skcipher.c
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+++ b/drivers/crypto/qce/skcipher.c
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@@ -5,6 +5,7 @@
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#include <linux/device.h>
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#include <linux/interrupt.h>
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+#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <crypto/aes.h>
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#include <crypto/internal/des.h>
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@@ -12,6 +13,13 @@
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#include "cipher.h"
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+static unsigned int aes_sw_max_len = CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN;
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+module_param(aes_sw_max_len, uint, 0644);
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+MODULE_PARM_DESC(aes_sw_max_len,
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+ "Only use hardware for AES requests larger than this "
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+ "[0=always use hardware; anything <16 breaks AES-GCM; default="
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+ __stringify(CONFIG_CRYPTO_DEV_QCE_SOFT_THRESHOLD)"]");
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+
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static LIST_HEAD(skcipher_algs);
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static void qce_skcipher_done(void *data)
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@@ -166,15 +174,10 @@ static int qce_skcipher_setkey(struct cr
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switch (IS_XTS(flags) ? keylen >> 1 : keylen) {
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case AES_KEYSIZE_128:
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case AES_KEYSIZE_256:
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+ memcpy(ctx->enc_key, key, keylen);
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break;
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- default:
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- goto fallback;
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}
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- ctx->enc_keylen = keylen;
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- memcpy(ctx->enc_key, key, keylen);
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- return 0;
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-fallback:
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ret = crypto_sync_skcipher_setkey(ctx->fallback, key, keylen);
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if (!ret)
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ctx->enc_keylen = keylen;
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@@ -224,8 +227,9 @@ static int qce_skcipher_crypt(struct skc
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rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
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keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen;
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- if (IS_AES(rctx->flags) && keylen != AES_KEYSIZE_128 &&
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- keylen != AES_KEYSIZE_256) {
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+ if (IS_AES(rctx->flags) &&
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+ ((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) ||
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+ req->cryptlen <= aes_sw_max_len)) {
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SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
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skcipher_request_set_sync_tfm(subreq, ctx->fallback);
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