mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 22:47:56 +00:00
454 lines
15 KiB
Diff
454 lines
15 KiB
Diff
From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
|
|
Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
|
|
From: Matthias Schiffer <mschiffer@universe-factory.net>
|
|
Date: Sat, 29 Mar 2014 20:26:08 +0100
|
|
Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
|
|
|
|
Note that the clock calculation looks very similar to the QCA955x, but the
|
|
meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
---
|
|
arch/mips/ath79/Kconfig | 6 +-
|
|
arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++++
|
|
arch/mips/ath79/common.c | 4 ++
|
|
arch/mips/ath79/dev-common.c | 1 +
|
|
arch/mips/ath79/dev-wmac.c | 20 +++++++
|
|
arch/mips/ath79/early_printk.c | 1 +
|
|
arch/mips/ath79/gpio.c | 4 +-
|
|
arch/mips/ath79/irq.c | 4 ++
|
|
arch/mips/ath79/setup.c | 8 ++-
|
|
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
|
|
arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++
|
|
11 files changed, 182 insertions(+), 3 deletions(-)
|
|
|
|
--- a/arch/mips/ath79/Kconfig
|
|
+++ b/arch/mips/ath79/Kconfig
|
|
@@ -1174,6 +1174,10 @@ config SOC_AR934X
|
|
select PCI_AR724X if PCI
|
|
def_bool n
|
|
|
|
+config SOC_QCA953X
|
|
+ select USB_ARCH_HAS_EHCI
|
|
+ def_bool n
|
|
+
|
|
config SOC_QCA955X
|
|
select HW_HAS_PCI
|
|
select PCI_AR724X if PCI
|
|
@@ -1216,7 +1220,7 @@ config ATH79_DEV_USB
|
|
def_bool n
|
|
|
|
config ATH79_DEV_WMAC
|
|
- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
|
|
+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
|
|
def_bool n
|
|
|
|
config ATH79_NVRAM
|
|
--- a/arch/mips/ath79/clock.c
|
|
+++ b/arch/mips/ath79/clock.c
|
|
@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(vo
|
|
iounmap(dpll_base);
|
|
}
|
|
|
|
+static void __init qca953x_clocks_init(void)
|
|
+{
|
|
+ unsigned long ref_rate;
|
|
+ unsigned long cpu_rate;
|
|
+ unsigned long ddr_rate;
|
|
+ unsigned long ahb_rate;
|
|
+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
|
|
+ u32 cpu_pll, ddr_pll;
|
|
+ u32 bootstrap;
|
|
+
|
|
+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
|
|
+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
|
|
+ ref_rate = 40 * 1000 * 1000;
|
|
+ else
|
|
+ ref_rate = 25 * 1000 * 1000;
|
|
+
|
|
+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
|
|
+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
|
|
+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
|
|
+ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
|
|
+ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
|
|
+ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
|
|
+ QCA953X_PLL_CPU_CONFIG_NINT_MASK;
|
|
+ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
|
|
+ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
|
|
+
|
|
+ cpu_pll = nint * ref_rate / ref_div;
|
|
+ cpu_pll += frac * (ref_rate >> 6) / ref_div;
|
|
+ cpu_pll /= (1 << out_div);
|
|
+
|
|
+ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
|
|
+ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
|
|
+ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
|
|
+ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
|
|
+ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
|
|
+ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
|
|
+ QCA953X_PLL_DDR_CONFIG_NINT_MASK;
|
|
+ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
|
|
+ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
|
|
+
|
|
+ ddr_pll = nint * ref_rate / ref_div;
|
|
+ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
|
|
+ ddr_pll /= (1 << out_div);
|
|
+
|
|
+ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
|
|
+
|
|
+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
|
|
+ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
|
|
+
|
|
+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
|
|
+ cpu_rate = ref_rate;
|
|
+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
|
|
+ cpu_rate = cpu_pll / (postdiv + 1);
|
|
+ else
|
|
+ cpu_rate = ddr_pll / (postdiv + 1);
|
|
+
|
|
+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
|
|
+ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
|
|
+
|
|
+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
|
|
+ ddr_rate = ref_rate;
|
|
+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
|
|
+ ddr_rate = ddr_pll / (postdiv + 1);
|
|
+ else
|
|
+ ddr_rate = cpu_pll / (postdiv + 1);
|
|
+
|
|
+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
|
|
+ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
|
|
+
|
|
+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
|
|
+ ahb_rate = ref_rate;
|
|
+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
|
|
+ ahb_rate = ddr_pll / (postdiv + 1);
|
|
+ else
|
|
+ ahb_rate = cpu_pll / (postdiv + 1);
|
|
+
|
|
+ ath79_add_sys_clkdev("ref", ref_rate);
|
|
+ ath79_add_sys_clkdev("cpu", cpu_rate);
|
|
+ ath79_add_sys_clkdev("ddr", ddr_rate);
|
|
+ ath79_add_sys_clkdev("ahb", ahb_rate);
|
|
+
|
|
+ clk_add_alias("wdt", NULL, "ref", NULL);
|
|
+ clk_add_alias("uart", NULL, "ref", NULL);
|
|
+}
|
|
+
|
|
static void __init qca955x_clocks_init(void)
|
|
{
|
|
unsigned long ref_rate;
|
|
@@ -447,6 +532,8 @@ void __init ath79_clocks_init(void)
|
|
ar933x_clocks_init();
|
|
else if (soc_is_ar934x())
|
|
ar934x_clocks_init();
|
|
+ else if (soc_is_qca953x())
|
|
+ qca953x_clocks_init();
|
|
else if (soc_is_qca955x())
|
|
qca955x_clocks_init();
|
|
else
|
|
--- a/arch/mips/ath79/common.c
|
|
+++ b/arch/mips/ath79/common.c
|
|
@@ -73,6 +73,8 @@ void ath79_device_reset_set(u32 mask)
|
|
reg = AR933X_RESET_REG_RESET_MODULE;
|
|
else if (soc_is_ar934x())
|
|
reg = AR934X_RESET_REG_RESET_MODULE;
|
|
+ else if (soc_is_qca953x())
|
|
+ reg = QCA953X_RESET_REG_RESET_MODULE;
|
|
else if (soc_is_qca955x())
|
|
reg = QCA955X_RESET_REG_RESET_MODULE;
|
|
else
|
|
@@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask)
|
|
reg = AR933X_RESET_REG_RESET_MODULE;
|
|
else if (soc_is_ar934x())
|
|
reg = AR934X_RESET_REG_RESET_MODULE;
|
|
+ else if (soc_is_qca953x())
|
|
+ reg = QCA953X_RESET_REG_RESET_MODULE;
|
|
else if (soc_is_qca955x())
|
|
reg = QCA955X_RESET_REG_RESET_MODULE;
|
|
else
|
|
--- a/arch/mips/ath79/dev-common.c
|
|
+++ b/arch/mips/ath79/dev-common.c
|
|
@@ -93,6 +93,7 @@ void __init ath79_register_uart(void)
|
|
soc_is_ar724x() ||
|
|
soc_is_ar913x() ||
|
|
soc_is_ar934x() ||
|
|
+ soc_is_qca953x() ||
|
|
soc_is_qca955x()) {
|
|
ath79_uart_data[0].uartclk = uart_clk_rate;
|
|
platform_device_register(&ath79_uart_device);
|
|
--- a/arch/mips/ath79/dev-wmac.c
|
|
+++ b/arch/mips/ath79/dev-wmac.c
|
|
@@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
-static int ar933x_r1_get_wmac_revision(void)
|
|
+static int ar93xx_get_soc_revision(void)
|
|
{
|
|
return ath79_soc_rev;
|
|
}
|
|
@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
|
|
ath79_wmac_data.is_clk_25mhz = true;
|
|
|
|
if (ath79_soc_rev == 1)
|
|
- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
|
|
+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
|
|
|
|
ath79_wmac_data.external_reset = ar933x_wmac_reset;
|
|
}
|
|
@@ -149,6 +149,26 @@ static void ar934x_wmac_setup(void)
|
|
ath79_wmac_data.is_clk_25mhz = true;
|
|
}
|
|
|
|
+static void qca953x_wmac_setup(void)
|
|
+{
|
|
+ u32 t;
|
|
+
|
|
+ ath79_wmac_device.name = "qca953x_wmac";
|
|
+
|
|
+ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
|
|
+ ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
|
|
+ ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
|
|
+ ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
|
|
+
|
|
+ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
|
|
+ if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
|
|
+ ath79_wmac_data.is_clk_25mhz = false;
|
|
+ else
|
|
+ ath79_wmac_data.is_clk_25mhz = true;
|
|
+
|
|
+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
|
|
+}
|
|
+
|
|
static void qca955x_wmac_setup(void)
|
|
{
|
|
u32 t;
|
|
@@ -366,6 +386,8 @@ void __init ath79_register_wmac(u8 *cal_
|
|
ar933x_wmac_setup();
|
|
else if (soc_is_ar934x())
|
|
ar934x_wmac_setup();
|
|
+ else if (soc_is_qca953x())
|
|
+ qca953x_wmac_setup();
|
|
else if (soc_is_qca955x())
|
|
qca955x_wmac_setup();
|
|
else
|
|
--- a/arch/mips/ath79/early_printk.c
|
|
+++ b/arch/mips/ath79/early_printk.c
|
|
@@ -114,6 +114,8 @@ static void prom_putchar_init(void)
|
|
case REV_ID_MAJOR_AR9341:
|
|
case REV_ID_MAJOR_AR9342:
|
|
case REV_ID_MAJOR_AR9344:
|
|
+ case REV_ID_MAJOR_QCA9533:
|
|
+ case REV_ID_MAJOR_QCA9533_V2:
|
|
case REV_ID_MAJOR_QCA9556:
|
|
case REV_ID_MAJOR_QCA9558:
|
|
_prom_putchar = prom_putchar_ar71xx;
|
|
--- a/arch/mips/ath79/gpio.c
|
|
+++ b/arch/mips/ath79/gpio.c
|
|
@@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
|
|
ath79_gpio_count = AR933X_GPIO_COUNT;
|
|
else if (soc_is_ar934x())
|
|
ath79_gpio_count = AR934X_GPIO_COUNT;
|
|
+ else if (soc_is_qca953x())
|
|
+ ath79_gpio_count = QCA953X_GPIO_COUNT;
|
|
else if (soc_is_qca955x())
|
|
ath79_gpio_count = QCA955X_GPIO_COUNT;
|
|
else
|
|
@@ -231,7 +233,7 @@ void __init ath79_gpio_init(void)
|
|
|
|
ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
|
|
ath79_gpio_chip.ngpio = ath79_gpio_count;
|
|
- if (soc_is_ar934x() || soc_is_qca955x()) {
|
|
+ if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
|
|
ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
|
|
ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
|
|
}
|
|
--- a/arch/mips/ath79/irq.c
|
|
+++ b/arch/mips/ath79/irq.c
|
|
@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
|
|
else if (soc_is_ar724x() ||
|
|
soc_is_ar933x() ||
|
|
soc_is_ar934x() ||
|
|
+ soc_is_qca953x() ||
|
|
soc_is_qca955x())
|
|
ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
|
|
else
|
|
@@ -352,6 +353,9 @@ void __init arch_init_irq(void)
|
|
} else if (soc_is_ar934x()) {
|
|
ath79_ip2_handler = ath79_default_ip2_handler;
|
|
ath79_ip3_handler = ar934x_ip3_handler;
|
|
+ } else if (soc_is_qca953x()) {
|
|
+ ath79_ip2_handler = ath79_default_ip2_handler;
|
|
+ ath79_ip3_handler = ath79_default_ip3_handler;
|
|
} else if (soc_is_qca955x()) {
|
|
ath79_ip2_handler = ath79_default_ip2_handler;
|
|
ath79_ip3_handler = ath79_default_ip3_handler;
|
|
--- a/arch/mips/ath79/setup.c
|
|
+++ b/arch/mips/ath79/setup.c
|
|
@@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
|
|
u32 major;
|
|
u32 minor;
|
|
u32 rev = 0;
|
|
+ u32 ver = 1;
|
|
|
|
id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
|
|
major = id & REV_ID_MAJOR_MASK;
|
|
@@ -151,6 +152,16 @@ static void __init ath79_detect_sys_type
|
|
rev = id & AR934X_REV_ID_REVISION_MASK;
|
|
break;
|
|
|
|
+ case REV_ID_MAJOR_QCA9533_V2:
|
|
+ ver = 2;
|
|
+ /* drop through */
|
|
+
|
|
+ case REV_ID_MAJOR_QCA9533:
|
|
+ ath79_soc = ATH79_SOC_QCA9533;
|
|
+ chip = "9533";
|
|
+ rev = id & QCA953X_REV_ID_REVISION_MASK;
|
|
+ break;
|
|
+
|
|
case REV_ID_MAJOR_QCA9556:
|
|
ath79_soc = ATH79_SOC_QCA9556;
|
|
chip = "9556";
|
|
@@ -169,9 +180,9 @@ static void __init ath79_detect_sys_type
|
|
|
|
ath79_soc_rev = rev;
|
|
|
|
- if (soc_is_qca955x())
|
|
- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
|
|
- chip, rev);
|
|
+ if (soc_is_qca953x() || soc_is_qca955x())
|
|
+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
|
|
+ chip, ver, rev);
|
|
else
|
|
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
|
|
pr_info("SoC: %s\n", ath79_sys_type);
|
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
@@ -105,6 +105,9 @@
|
|
#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
|
|
#define AR934X_SRIF_SIZE 0x1000
|
|
|
|
+#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
|
|
+#define QCA953X_WMAC_SIZE 0x20000
|
|
+
|
|
#define QCA955X_PCI_MEM_BASE0 0x10000000
|
|
#define QCA955X_PCI_MEM_BASE1 0x12000000
|
|
#define QCA955X_PCI_MEM_SIZE 0x02000000
|
|
@@ -279,6 +282,43 @@
|
|
|
|
#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
|
|
|
|
+#define QCA953X_PLL_CPU_CONFIG_REG 0x00
|
|
+#define QCA953X_PLL_DDR_CONFIG_REG 0x04
|
|
+#define QCA953X_PLL_CLK_CTRL_REG 0x08
|
|
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
|
|
+#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
|
|
+
|
|
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
|
|
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
|
|
+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
|
|
+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
|
|
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
|
|
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
|
|
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
|
|
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
|
|
+
|
|
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
|
|
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
|
|
+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
|
|
+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
|
|
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
|
|
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
|
|
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
|
|
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
|
|
+
|
|
+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
|
|
+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
|
|
+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
|
|
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
|
|
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
|
|
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
|
|
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
|
|
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
|
|
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
|
|
+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
|
|
+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
|
|
+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
|
|
+
|
|
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
|
|
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
|
|
#define QCA955X_PLL_CLK_CTRL_REG 0x08
|
|
@@ -355,6 +395,10 @@
|
|
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
|
|
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
|
|
|
|
+#define QCA953X_RESET_REG_RESET_MODULE 0x1c
|
|
+#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
|
|
+#define QCA953X_RESET_REG_EXT_INT_STATUS 0xac
|
|
+
|
|
#define QCA955X_RESET_REG_RESET_MODULE 0x1c
|
|
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
|
|
#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
|
|
@@ -503,6 +547,8 @@
|
|
#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
|
|
#define AR934X_BOOTSTRAP_DDR1 BIT(0)
|
|
|
|
+#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
|
+
|
|
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
|
|
|
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
|
|
@@ -565,6 +611,8 @@
|
|
#define REV_ID_MAJOR_AR9341 0x0120
|
|
#define REV_ID_MAJOR_AR9342 0x1120
|
|
#define REV_ID_MAJOR_AR9344 0x2120
|
|
+#define REV_ID_MAJOR_QCA9533 0x0140
|
|
+#define REV_ID_MAJOR_QCA9533_V2 0x0160
|
|
#define REV_ID_MAJOR_QCA9556 0x0130
|
|
#define REV_ID_MAJOR_QCA9558 0x1130
|
|
|
|
@@ -587,6 +635,8 @@
|
|
|
|
#define AR934X_REV_ID_REVISION_MASK 0xf
|
|
|
|
+#define QCA953X_REV_ID_REVISION_MASK 0xf
|
|
+
|
|
#define QCA955X_REV_ID_REVISION_MASK 0xf
|
|
|
|
/*
|
|
@@ -640,6 +690,7 @@
|
|
#define AR913X_GPIO_COUNT 22
|
|
#define AR933X_GPIO_COUNT 30
|
|
#define AR934X_GPIO_COUNT 23
|
|
+#define QCA953X_GPIO_COUNT 24
|
|
#define QCA955X_GPIO_COUNT 24
|
|
|
|
/*
|
|
--- a/arch/mips/include/asm/mach-ath79/ath79.h
|
|
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
|
@@ -32,6 +32,7 @@ enum ath79_soc_type {
|
|
ATH79_SOC_AR9341,
|
|
ATH79_SOC_AR9342,
|
|
ATH79_SOC_AR9344,
|
|
+ ATH79_SOC_QCA9533,
|
|
ATH79_SOC_QCA9556,
|
|
ATH79_SOC_QCA9558,
|
|
};
|
|
@@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
|
|
return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
|
|
}
|
|
|
|
+static inline int soc_is_qca9533(void)
|
|
+{
|
|
+ return ath79_soc == ATH79_SOC_QCA9533;
|
|
+}
|
|
+
|
|
+static inline int soc_is_qca953x(void)
|
|
+{
|
|
+ return soc_is_qca9533();
|
|
+}
|
|
+
|
|
static inline int soc_is_qca9556(void)
|
|
{
|
|
return ath79_soc == ATH79_SOC_QCA9556;
|