mirror of
https://github.com/openwrt/openwrt.git
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81995a5e77
All patches automatically rebased.
Build system: x86_64
Build-tested: ramips/mt7621*
*I am hit with the binutils 2.37 bug so I had to revert 7f1edbd412
in order to downgrade to 2.35.1
Signed-off-by: John Audia <graysky@archlinux.us>
157 lines
4.2 KiB
Diff
157 lines
4.2 KiB
Diff
From a9f1c1d3e410596d0a39fd92562cc48ef960b1b7 Mon Sep 17 00:00:00 2001
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From: Li Yang <leoyang.li@nxp.com>
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Date: Fri, 5 Oct 2018 18:33:49 -0500
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Subject: [PATCH] ARM: dts: accumulated change
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Signed-off-by: Li Yang <leoyang.li@nxp.com>
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---
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arch/arm/boot/dts/ls1021a-qds.dts | 15 +++++++++++++++
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arch/arm/boot/dts/ls1021a-twr.dts | 15 +++++++++++++++
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arch/arm/boot/dts/ls1021a.dtsi | 29 ++++++++++++++++++++++++-----
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3 files changed, 54 insertions(+), 5 deletions(-)
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--- a/arch/arm/boot/dts/ls1021a-qds.dts
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+++ b/arch/arm/boot/dts/ls1021a-qds.dts
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@@ -126,6 +126,21 @@
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};
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};
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+&qspi {
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+ num-cs = <2>;
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+ status = "okay";
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+
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+ qflash0: s25fl128s@0 {
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+ compatible = "spansion,m25p80";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ reg = <0>;
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+ spi-rx-bus-width = <4>;
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+ spi-tx-bus-width = <4>;
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+ };
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+};
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+
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&enet0 {
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tbi-handle = <&tbi0>;
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phy-handle = <&sgmii_phy1c>;
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--- a/arch/arm/boot/dts/ls1021a-twr.dts
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+++ b/arch/arm/boot/dts/ls1021a-twr.dts
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@@ -144,6 +144,21 @@
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};
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};
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+&qspi {
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+ num-cs = <2>;
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+ status = "okay";
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+
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+ qflash0: n25q128a13@0 {
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+ compatible = "n25q128a13", "jedec,spi-nor";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ reg = <0>;
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+ spi-rx-bus-width = <4>;
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+ spi-tx-bus-width = <4>;
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+ };
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+};
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+
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&enet0 {
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tbi-handle = <&tbi0>;
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phy-handle = <&sgmii_phy2>;
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--- a/arch/arm/boot/dts/ls1021a.dtsi
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+++ b/arch/arm/boot/dts/ls1021a.dtsi
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@@ -167,12 +167,13 @@
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ifc: ifc@1530000 {
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compatible = "fsl,ifc", "simple-bus";
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reg = <0x0 0x1530000 0x0 0x10000>;
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+ big-endian;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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};
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dcfg: dcfg@1ee0000 {
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compatible = "fsl,ls1021a-dcfg", "syscon";
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- reg = <0x0 0x1ee0000 0x0 0x10000>;
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+ reg = <0x0 0x1ee0000 0x0 0x1000>;
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big-endian;
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};
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@@ -338,7 +339,7 @@
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};
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i2c0: i2c@2180000 {
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- compatible = "fsl,vf610-i2c";
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+ compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2180000 0x0 0x10000>;
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@@ -347,11 +348,12 @@
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clocks = <&clockgen 4 1>;
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dma-names = "tx", "rx";
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dmas = <&edma0 1 39>, <&edma0 1 38>;
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+ fsl-scl-gpio = <&gpio3 23 0>;
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status = "disabled";
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};
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i2c1: i2c@2190000 {
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- compatible = "fsl,vf610-i2c";
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+ compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2190000 0x0 0x10000>;
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@@ -360,6 +362,7 @@
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clocks = <&clockgen 4 1>;
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dma-names = "tx", "rx";
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dmas = <&edma0 1 37>, <&edma0 1 36>;
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+ fsl-scl-gpio = <&gpio3 23 0>;
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status = "disabled";
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};
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@@ -546,6 +549,16 @@
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status = "disabled";
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};
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+ ftm0: ftm0@29d0000 {
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+ compatible = "fsl,ftm-alarm";
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+ reg = <0x0 0x29d0000 0x0 0x10000>,
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+ <0x0 0x1ee2140 0x0 0x4>;
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+ reg-names = "ftm", "FlexTimer1";
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+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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+ big-endian;
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+ status = "okay";
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+ };
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+
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pwm1: pwm@29e0000 {
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compatible = "fsl,vf610-ftm-pwm";
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#pwm-cells = <3>;
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@@ -828,6 +841,8 @@
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dr_mode = "host";
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snps,quirk-frame-length-adjustment = <0x20>;
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snps,dis_rxdet_inp3_quirk;
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+ usb3-lpm-capable;
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+ snps,dis-u1u2-when-u3-quirk;
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snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
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};
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@@ -836,7 +851,9 @@
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reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
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0x40 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
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+ interrupt-names = "pme", "aer";
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fsl,pcie-scfg = <&scfg 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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@@ -860,7 +877,9 @@
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reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
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0x48 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
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+ interrupt-names = "pme", "aer";
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fsl,pcie-scfg = <&scfg 1>;
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#address-cells = <3>;
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#size-cells = <2>;
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