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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
47 lines
1.9 KiB
Diff
47 lines
1.9 KiB
Diff
From 8df9fefd1d04f6f97f6015d7347104f69e6ea580 Mon Sep 17 00:00:00 2001
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From: Baruch Siach <baruch.siach@siklu.com>
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Date: Tue, 21 Jun 2022 11:54:52 +0300
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Subject: [PATCH] PCI: dwc: Move GEN3_RELATED DBI definitions to common header
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These are common dwc macros that will be used for other platforms.
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Link: https://lore.kernel.org/r/1c2d5a7a139be81fa15f356b2380163dbdebdc09.1655799816.git.baruch@tkos.co.il
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Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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---
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drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++
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drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
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2 files changed, 6 insertions(+), 6 deletions(-)
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--- a/drivers/pci/controller/dwc/pcie-designware.h
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+++ b/drivers/pci/controller/dwc/pcie-designware.h
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@@ -74,6 +74,12 @@
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#define PCIE_MSI_INTR0_MASK 0x82C
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#define PCIE_MSI_INTR0_STATUS 0x830
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+#define GEN3_RELATED_OFF 0x890
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+#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
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+#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
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+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
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+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
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+
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#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
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#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
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--- a/drivers/pci/controller/dwc/pcie-tegra194.c
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+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
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@@ -193,12 +193,6 @@
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#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
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#define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
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-#define GEN3_RELATED_OFF 0x890
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-#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
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-#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
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-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
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-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
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-
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#define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
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#define AMBA_ERROR_RESPONSE_CRS_SHIFT 3
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#define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)
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