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192 lines
4.7 KiB
Diff
192 lines
4.7 KiB
Diff
From 1ba56aeb391401c4cb2126c39f90b3cdbfabdb3f Mon Sep 17 00:00:00 2001
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From: William Zhang <william.zhang@broadcom.com>
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Date: Wed, 1 Jun 2022 13:17:34 -0700
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Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM4912
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Add DTS for ARMv8 based broadband SoC BCM4912. bcm4912.dtsi is the
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SoC description DTS header and bcm94912.dts is a simple DTS file for
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Broadcom BCM94912 Reference board that only enable the UART port.
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Signed-off-by: William Zhang <william.zhang@broadcom.com>
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Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
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.../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 128 ++++++++++++++++++
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.../boot/dts/broadcom/bcmbca/bcm94912.dts | 30 ++++
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3 files changed, 160 insertions(+), 1 deletion(-)
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create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
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create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
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@@ -1,2 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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-dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb
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+dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
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+ bcm963158.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
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@@ -0,0 +1,128 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright 2022 Broadcom Ltd.
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+ */
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+
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+#include <dt-bindings/interrupt-controller/irq.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+
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+/ {
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+ compatible = "brcm,bcm4912", "brcm,bcmbca";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ interrupt-parent = <&gic>;
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+
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+ cpus {
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+ #address-cells = <2>;
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+ #size-cells = <0>;
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+
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+ B53_0: cpu@0 {
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+ compatible = "brcm,brahma-b53";
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+ device_type = "cpu";
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+ reg = <0x0 0x0>;
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+ next-level-cache = <&L2_0>;
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+ enable-method = "psci";
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+ };
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+
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+ B53_1: cpu@1 {
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+ compatible = "brcm,brahma-b53";
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+ device_type = "cpu";
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+ reg = <0x0 0x1>;
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+ next-level-cache = <&L2_0>;
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+ enable-method = "psci";
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+ };
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+
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+ B53_2: cpu@2 {
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+ compatible = "brcm,brahma-b53";
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+ device_type = "cpu";
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+ reg = <0x0 0x2>;
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+ next-level-cache = <&L2_0>;
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+ enable-method = "psci";
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+ };
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+
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+ B53_3: cpu@3 {
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+ compatible = "brcm,brahma-b53";
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+ device_type = "cpu";
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+ reg = <0x0 0x3>;
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+ next-level-cache = <&L2_0>;
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+ enable-method = "psci";
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+ };
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+
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+ L2_0: l2-cache0 {
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+ compatible = "cache";
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+ };
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+ };
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+
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+ timer {
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+ compatible = "arm,armv8-timer";
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+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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+ };
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+
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+ pmu: pmu {
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+ compatible = "arm,cortex-a53-pmu";
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+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-affinity = <&B53_0>, <&B53_1>,
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+ <&B53_2>, <&B53_3>;
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+ };
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+
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+ clocks: clocks {
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+ periph_clk: periph-clk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <200000000>;
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+ };
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+ uart_clk: uart-clk {
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+ compatible = "fixed-factor-clock";
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+ #clock-cells = <0>;
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+ clocks = <&periph_clk>;
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+ clock-div = <4>;
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+ clock-mult = <1>;
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+ };
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+ };
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+
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+ psci {
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+ compatible = "arm,psci-0.2";
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+ method = "smc";
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+ };
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+
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+ axi@81000000 {
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+ compatible = "simple-bus";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0x0 0x0 0x81000000 0x8000>;
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+
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+ gic: interrupt-controller@1000 {
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+ compatible = "arm,gic-400";
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+ #interrupt-cells = <3>;
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+ interrupt-controller;
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+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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+ reg = <0x1000 0x1000>,
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+ <0x2000 0x2000>,
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+ <0x4000 0x2000>,
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+ <0x6000 0x2000>;
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+ };
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+ };
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+
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+ bus@ff800000 {
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+ compatible = "simple-bus";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0x0 0x0 0xff800000 0x800000>;
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+
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+ uart0: serial@12000 {
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+ compatible = "arm,pl011", "arm,primecell";
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+ reg = <0x12000 0x1000>;
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+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&uart_clk>, <&uart_clk>;
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+ clock-names = "uartclk", "apb_pclk";
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+ status = "disabled";
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
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@@ -0,0 +1,30 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright 2022 Broadcom Ltd.
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+ */
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+
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+/dts-v1/;
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+
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+#include "bcm4912.dtsi"
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+
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+/ {
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+ model = "Broadcom BCM94912 Reference Board";
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+ compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";
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+
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+ aliases {
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+ serial0 = &uart0;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ memory@0 {
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+ device_type = "memory";
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+ reg = <0x0 0x0 0x0 0x08000000>;
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+ };
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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