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029093a302
This target has full device tree support, thus reducing the number of patches needed for bcm63xx, in which there's a patch for every board. The intention is to start with a minimal amount of downstream patches and start upstreaming all of them. Current status: - Enabling EHCI/OHCI on BCM6358 causes a kernel panic. - BCM63268 lacks Timer Clocks/Reset support. - No PCI/PCIe drivers. - No ethernet drivers. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
87 lines
2.8 KiB
C
87 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM63268_H
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#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM63268_H
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#define BCM63268_IRQ_TIMER 0
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#define BCM63268_IRQ_ENETSW_RX_DMA0 1
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#define BCM63268_IRQ_ENETSW_RX_DMA1 2
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#define BCM63268_IRQ_ENETSW_RX_DMA2 3
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#define BCM63268_IRQ_ENETSW_RX_DMA3 4
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#define BCM63268_IRQ_UART0 5
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#define BCM63268_IRQ_HSSPI 6
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#define BCM63268_IRQ_WLAN 7
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#define BCM63268_IRQ_IPSEC 8
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#define BCM63268_IRQ_OHCI 9
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#define BCM63268_IRQ_EHCI 10
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#define BCM63268_IRQ_USBS 11
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#define BCM63268_IRQ_PCM 12
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#define BCM63268_IRQ_EPHY 13
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#define BCM63268_IRQ_DG 14
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#define BCM63268_IRQ_EPHY0_EN 15
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#define BCM63268_IRQ_EPHY1_EN 16
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#define BCM63268_IRQ_EPHY2_EN 17
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#define BCM63268_IRQ_GPHY_EN 18
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#define BCM63268_IRQ_USB_CTL_RX_DMA 19
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#define BCM63268_IRQ_USB_BULK_RX_DMA 20
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#define BCM63268_IRQ_ISO_RX_DMA 21
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#define BCM63268_IRQ_IPSEC_DMA0 22
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#define BCM63268_IRQ_XDSL 23
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#define BCM63268_IRQ_FAP0 24
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#define BCM63268_IRQ_FAP1 25
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#define BCM63268_IRQ_ATM_DMA0 26
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#define BCM63268_IRQ_ATM_DMA1 27
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#define BCM63268_IRQ_ATM_DMA2 28
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#define BCM63268_IRQ_ATM_DMA3 29
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#define BCM63268_IRQ_WAKE_ON_IRQ 30
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#define BCM63268_IRQ_GPHY 31
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#define BCM63268_IRQ_DECT0 32
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#define BCM63268_IRQ_DECT1 33
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#define BCM63268_IRQ_UART1 34
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#define BCM63268_IRQ_WLAN_GPIO 35
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#define BCM63268_IRQ_USB_CTL_TX_DMA 36
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#define BCM63268_IRQ_USB_BULK_TX_DMA 37
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#define BCM63268_IRQ_ISO_TX_DMA 38
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#define BCM63268_IRQ_IPSEC_DMA1 39
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#define BCM63268_IRQ_PCIE_RC 40
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#define BCM63268_IRQ_PCIE_EP 41
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#define BCM63268_IRQ_PCM_DMA0 42
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#define BCM63268_IRQ_PCM_DMA1 43
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#define BCM63268_IRQ_EXT0 44
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#define BCM63268_IRQ_EXT1 45
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#define BCM63268_IRQ_EXT2 46
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#define BCM63268_IRQ_EXT3 47
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#define BCM63268_IRQ_ENETSW 48
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#define BCM63268_IRQ_SAR 49
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#define BCM63268_IRQ_NAND 50
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#define BCM63268_IRQ_RING_OSC 52
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#define BCM63268_IRQ_USB_CONNECT 53
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#define BCM63268_IRQ_USB_DISCONNECT 54
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#define BCM63268_IRQ_PER_MBOX0 55
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#define BCM63268_IRQ_PER_MBOX1 56
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#define BCM63268_IRQ_PER_MBOX2 57
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#define BCM63268_IRQ_PER_MBOX3 58
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#define BCM63268_IRQ_ATM_DMA4 59
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#define BCM63268_IRQ_ATM_DMA5 60
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#define BCM63268_IRQ_ATM_DMA6 61
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#define BCM63268_IRQ_ATM_DMA7 62
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#define BCM63268_IRQ_ENETSW_TX_DMA0 64
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#define BCM63268_IRQ_ENETSW_TX_DMA1 65
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#define BCM63268_IRQ_ENETSW_TX_DMA2 66
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#define BCM63268_IRQ_ENETSW_TX_DMA3 67
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#define BCM63268_IRQ_ATM_DMA8 68
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#define BCM63268_IRQ_ATM_DMA9 69
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#define BCM63268_IRQ_ATM_DMA10 70
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#define BCM63268_IRQ_ATM_DMA11 71
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#define BCM63268_IRQ_ATM_DMA12 72
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#define BCM63268_IRQ_ATM_DMA13 73
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#define BCM63268_IRQ_ATM_DMA14 74
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#define BCM63268_IRQ_ATM_DMA15 75
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#define BCM63268_IRQ_ATM_DMA16 76
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#define BCM63268_IRQ_ATM_DMA17 77
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#define BCM63268_IRQ_ATM_DMA18 78
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#define BCM63268_IRQ_ATM_DMA19 79
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#define BCM63268_IRQ_LSSPI 80
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#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM63268_H */
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