openwrt/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi
Adrian Schmutzler 3a4b751110 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-02-24 02:53:53 +01:00

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qca956x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
keys {
compatible = "gpio-keys";
wps {
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
reset {
linux,code = <KEY_RESTART>;
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "green:power";
gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
};
wps {
label = "green:wps";
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
};
wlan {
label = "green:wlan";
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
};
};
&pcie {
status = "okay";
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x40000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x040000 0x10000>;
read-only;
};
partition@50000 {
label = "devdata";
reg = <0x050000 0x10000>;
read-only;
};
partition@60000 {
label = "devconf";
reg = <0x060000 0x10000>;
read-only;
};
partition@70000 {
label = "misc";
reg = <0x070000 0x10000>;
read-only;
};
partition@80000 {
compatible = "seama";
label = "firmware";
reg = <0x080000 0xf50000>;
};
art: partition@fd0000 {
label = "art";
reg = <0xfd0000 0x010000>;
read-only;
};
partition@fe0000 {
label = "reserved";
reg = <0xfe0000 0x20000>;
read-only;
};
};
};
};
&mdio0 {
status = "okay";
phy-mask = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
qca,mib-poll-interval = <500>;
reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
qca,ar8327-initvals = <
0x04 0x00080080 /* PORT0 PAD MODE CTRL */
0x10 0x81000080 /* POWER_ON_STRAP */
0x50 0xcc35cc35 /* LED_CTRL0 */
0x54 0xcb37cb37 /* LED_CTRL1 */
0x58 0x00000000 /* LED_CTRL2 */
0x5c 0x00f3cf00 /* LED_CTRL3 */
0x7c 0x0000007e /* PORT0_STATUS */
>;
};
};
&eth0 {
status = "okay";
pll-data = <0x03000101 0x00000101 0x00001919>;
phy-mode = "sgmii";
phy-handle = <&phy0>;
};
&wmac {
status = "okay";
qca,no-eeprom;
};