openwrt/target/linux/ath79/dts/ar9344_wd_mynet-n750.dts
Adrian Schmutzler 3a4b751110 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-02-24 02:53:53 +01:00

210 lines
3.1 KiB
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ar9344.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Western Digital My Net N750";
compatible = "wd,mynet-n750", "qca,ar9344";
chosen {
bootargs = "console=ttyS0,115200n8";
};
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
leds {
compatible = "gpio-leds";
wifi {
label = "blue:wireless";
gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
};
internet {
label = "blue:internet";
gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
};
wps {
label = "blue:wps";
gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
};
led_power: power {
label = "blue:power";
gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
};
};
keys {
compatible = "gpio-keys";
reset {
linux,code = <KEY_RESTART>;
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
};
wps {
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
};
};
};
&ref {
clock-frequency = <40000000>;
};
&gpio {
gpio_ext_lna0 {
gpio-hog;
gpios = <15 0>;
output-high;
line-name = "mynet-n750:ext:lna0";
};
gpio_ext_lna1 {
gpio-hog;
gpios = <18 0>;
output-high;
line-name = "mynet-n750:ext:lna1";
};
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x000000 0x40000>;
read-only;
};
partition@40000 {
label = "bdcfg";
reg = <0x040000 0x10000>;
read-only;
};
partition@50000 {
label = "devdata";
reg = <0x050000 0x10000>;
read-only;
};
partition@60000 {
label = "devconf";
reg = <0x060000 0x10000>;
read-only;
};
partition@70000 {
compatible = "seama";
label = "firmware";
reg = <0x070000 0xf80000>;
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&usb {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
#trigger-source-cells = <0>;
hub_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
hub_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
&usb_phy {
status = "okay";
};
&pcie {
status = "okay";
wifi@0,0 {
compatible = "pci168c,0033";
reg = <0x0000 0 0 0 0>;
qca,no-eeprom;
};
};
&wmac {
status = "okay";
qca,no-eeprom;
};
&mdio0 {
status = "okay";
phy-mask = <0>;
switch0@1f {
compatible = "qca,ar8327";
reg = <0x1f>;
qca,ar8327-initvals = <
0x04 0x07600000 /* PORT0 PAD MODE CTRL */
0x10 0x80000080 /* POWER_ON_STRAP */
0x50 0xc737c737 /* LED_CTRL0 */
0x54 0x00000000 /* LED_CTRL1 */
0x58 0x00000000 /* LED_CTRL2 */
0x5c 0x0030c300 /* LED_CTRL3 */
0x7c 0x0000007e /* PORT0_STATUS */
>;
};
};
&eth0 {
status = "okay";
/* default for ar934x, except for 1000M */
pll-data = <0x06000000 0x00000101 0x00001616>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};