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c6c731fe31
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
67 lines
2.0 KiB
Diff
67 lines
2.0 KiB
Diff
From 61959c53020fff0584d88e28d6dae9806184f1a8 Mon Sep 17 00:00:00 2001
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From: Minghuan Lian <Minghuan.Lian@nxp.com>
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Date: Mon, 29 Feb 2016 17:24:15 -0600
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Subject: [PATCH 50/70] PCI: layerscape: Fix MSG TLP drop setting
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Some kinds of Layerscape PCIe controllers will forward the received message
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TLPs to system application address space, which could corrupt system memory
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or lead to a system hang. Enable MSG_DROP to fix this issue.
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Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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---
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drivers/pci/host/pci-layerscape.c | 21 +++++++++++++--------
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1 file changed, 13 insertions(+), 8 deletions(-)
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--- a/drivers/pci/host/pci-layerscape.c
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+++ b/drivers/pci/host/pci-layerscape.c
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@@ -77,6 +77,16 @@ static void ls_pcie_fix_class(struct ls_
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iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
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}
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+/* Drop MSG TLP except for Vendor MSG */
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+static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
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+{
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+ u32 val;
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+
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+ val = ioread32(pcie->dbi + PCIE_STRFMR1);
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+ val &= 0xDFFFFFFF;
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+ iowrite32(val, pcie->dbi + PCIE_STRFMR1);
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+}
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+
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static int ls1021_pcie_link_up(struct pcie_port *pp)
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{
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u32 state;
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@@ -97,7 +107,7 @@ static int ls1021_pcie_link_up(struct pc
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static void ls1021_pcie_host_init(struct pcie_port *pp)
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{
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struct ls_pcie *pcie = to_ls_pcie(pp);
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- u32 val, index[2];
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+ u32 index[2];
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pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node,
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"fsl,pcie-scfg");
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@@ -116,13 +126,7 @@ static void ls1021_pcie_host_init(struct
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dw_pcie_setup_rc(pp);
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- /*
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- * LS1021A Workaround for internal TKT228622
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- * to fix the INTx hang issue
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- */
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- val = ioread32(pcie->dbi + PCIE_STRFMR1);
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- val &= 0xffff;
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- iowrite32(val, pcie->dbi + PCIE_STRFMR1);
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+ ls_pcie_drop_msg_tlp(pcie);
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}
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static int ls_pcie_link_up(struct pcie_port *pp)
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@@ -147,6 +151,7 @@ static void ls_pcie_host_init(struct pci
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iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
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ls_pcie_fix_class(pcie);
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ls_pcie_clear_multifunction(pcie);
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+ ls_pcie_drop_msg_tlp(pcie);
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iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
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}
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