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207 lines
5.9 KiB
Diff
207 lines
5.9 KiB
Diff
From 6f5002c91f35f6b171bc608b87b3f2b55451f32b Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Sun, 3 Nov 2013 10:30:13 +0100
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Subject: [PATCH] ARM: sun6i: Add SMP support for the Allwinner A31
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The A31 is a quad Cortex-A7. Add the logic to use the IPs used to
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control the CPU configuration and the CPU power so that we can bring up
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secondary CPUs at boot.
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/mach-sunxi/Makefile | 1 +
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arch/arm/mach-sunxi/common.h | 19 +++++++
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arch/arm/mach-sunxi/headsmp.S | 9 +++
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arch/arm/mach-sunxi/platsmp.c | 124 ++++++++++++++++++++++++++++++++++++++++++
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arch/arm/mach-sunxi/sunxi.c | 3 +
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5 files changed, 156 insertions(+)
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create mode 100644 arch/arm/mach-sunxi/common.h
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create mode 100644 arch/arm/mach-sunxi/headsmp.S
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create mode 100644 arch/arm/mach-sunxi/platsmp.c
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--- a/arch/arm/mach-sunxi/Makefile
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+++ b/arch/arm/mach-sunxi/Makefile
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@@ -1 +1,2 @@
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obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
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+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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--- /dev/null
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+++ b/arch/arm/mach-sunxi/common.h
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@@ -0,0 +1,19 @@
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+/*
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+ * Core functions for Allwinner SoCs
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+ *
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+ * Copyright (C) 2013 Maxime Ripard
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+ *
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+ * Maxime Ripard <maxime.ripard@free-electrons.com>
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+#ifndef __ARCH_SUNXI_COMMON_H_
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+#define __ARCH_SUNXI_COMMON_H_
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+
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+void sun6i_secondary_startup(void);
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+extern struct smp_operations sun6i_smp_ops;
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+
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+#endif /* __ARCH_SUNXI_COMMON_H_ */
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--- /dev/null
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+++ b/arch/arm/mach-sunxi/headsmp.S
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@@ -0,0 +1,9 @@
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+#include <linux/linkage.h>
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+#include <linux/init.h>
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+
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+ .section ".text.head", "ax"
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+
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+ENTRY(sun6i_secondary_startup)
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+ msr cpsr_fsxc, #0xd3
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+ b secondary_startup
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+ENDPROC(sun6i_secondary_startup)
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--- /dev/null
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+++ b/arch/arm/mach-sunxi/platsmp.c
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@@ -0,0 +1,124 @@
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+/*
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+ * SMP support for Allwinner SoCs
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+ *
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+ * Copyright (C) 2013 Maxime Ripard
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+ *
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+ * Maxime Ripard <maxime.ripard@free-electrons.com>
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+ *
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+ * Based on code
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+ * Copyright (C) 2012-2013 Allwinner Ltd.
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+#include <linux/delay.h>
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/memory.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/smp.h>
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+
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+#include "common.h"
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+
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+#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
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+#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
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+#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
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+#define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08)
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+#define CPUCFG_GEN_CTRL_REG 0x184
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+#define CPUCFG_PRIVATE0_REG 0x1a4
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+#define CPUCFG_PRIVATE1_REG 0x1a8
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+#define CPUCFG_DBG_CTL0_REG 0x1e0
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+#define CPUCFG_DBG_CTL1_REG 0x1e4
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+
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+#define PRCM_CPU_PWROFF_REG 0x100
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+#define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140)
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+
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+static void __iomem *cpucfg_membase;
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+static void __iomem *prcm_membase;
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+
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+static DEFINE_SPINLOCK(cpu_lock);
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+
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+static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
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+{
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+ struct device_node *node;
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+
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+ node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
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+ if (!node) {
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+ pr_err("Missing A31 PRCM node in the device tree\n");
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+ return;
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+ }
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+
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+ prcm_membase = of_iomap(node, 0);
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+ if (!prcm_membase) {
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+ pr_err("Couldn't map A31 PRCM registers\n");
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+ return;
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+ }
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+
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+ node = of_find_compatible_node(NULL, NULL,
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+ "allwinner,sun6i-a31-cpuconfig");
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+ if (!node) {
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+ pr_err("Missing A31 CPU config node in the device tree\n");
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+ return;
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+ }
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+
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+ cpucfg_membase = of_iomap(node, 0);
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+ if (!cpucfg_membase)
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+ pr_err("Couldn't map A31 CPU config registers\n");
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+
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+}
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+
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+static int sun6i_smp_boot_secondary(unsigned int cpu,
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+ struct task_struct *idle)
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+{
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+ u32 reg;
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+ int i;
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+
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+ if (!(prcm_membase && cpucfg_membase))
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+ return -EFAULT;
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+
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+ spin_lock(&cpu_lock);
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+
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+ /* Set CPU boot address */
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+ writel(virt_to_phys(sun6i_secondary_startup),
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+ cpucfg_membase + CPUCFG_PRIVATE0_REG);
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+
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+ /* Assert the CPU core in reset */
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+ writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
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+
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+ /* Assert the L1 cache in reset */
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+ reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
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+ writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
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+
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+ /* Disable external debug access */
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+ reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
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+ writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
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+
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+ /* Power up the CPU */
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+ for (i = 0; i <= 8; i++)
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+ writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
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+ mdelay(10);
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+
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+ /* Clear CPU power-off gating */
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+ reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
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+ writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
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+ mdelay(1);
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+
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+ /* Deassert the CPU core reset */
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+ writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
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+
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+ /* Enable back the external debug accesses */
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+ reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
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+ writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
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+
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+ spin_unlock(&cpu_lock);
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+
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+ return 0;
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+}
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+
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+struct smp_operations sun6i_smp_ops __initdata = {
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+ .smp_prepare_cpus = sun6i_smp_prepare_cpus,
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+ .smp_boot_secondary = sun6i_smp_boot_secondary,
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+};
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--- a/arch/arm/mach-sunxi/sunxi.c
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+++ b/arch/arm/mach-sunxi/sunxi.c
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@@ -25,6 +25,8 @@
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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+#include "common.h"
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+
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#define SUN4I_WATCHDOG_CTRL_REG 0x00
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#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
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#define SUN4I_WATCHDOG_MODE_REG 0x04
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@@ -147,6 +149,7 @@ DT_MACHINE_START(SUN6I_DT, "Allwinner su
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.init_time = sun6i_timer_init,
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.dt_compat = sun6i_board_dt_compat,
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.restart = sun6i_restart,
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+ .smp = smp_ops(sun6i_smp_ops),
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MACHINE_END
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static const char * const sun7i_board_dt_compat[] = {
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