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296 lines
7.4 KiB
C
296 lines
7.4 KiB
C
/******************************************************************************
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**
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** FILE NAME : ifxmips_ptm_vr9.c
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** PROJECT : UEIP
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** MODULES : PTM
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**
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** DATE : 7 Jul 2009
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** AUTHOR : Xu Liang
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** DESCRIPTION : PTM driver common source file (core functions)
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** COPYRIGHT : Copyright (c) 2006
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Date $Author $Comment
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** 07 JUL 2009 Xu Liang Init Version
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*******************************************************************************/
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/*
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* ####################################
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* Head File
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* ####################################
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*/
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/*
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* Common Head File
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/version.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/proc_fs.h>
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#include <linux/init.h>
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#include <linux/ioctl.h>
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#include <asm/delay.h>
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/*
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* Chip Specific Head File
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*/
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#include "ifxmips_ptm_vdsl.h"
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#include "ifxmips_ptm_fw_vr9.h"
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#include <lantiq_soc.h>
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static inline void init_pmu(void);
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static inline void uninit_pmu(void);
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static inline void reset_ppe(void);
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static inline void init_pdma(void);
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static inline void init_mailbox(void);
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static inline void init_atm_tc(void);
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static inline void clear_share_buffer(void);
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#define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
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#define IFX_PMU_MODULE_PPE_TC BIT(21)
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#define IFX_PMU_MODULE_PPE_EMA BIT(22)
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#define IFX_PMU_MODULE_PPE_QSB BIT(18)
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#define IFX_PMU_MODULE_AHBS BIT(13)
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#define IFX_PMU_MODULE_DSL_DFE BIT(9)
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static inline void init_pmu(void)
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{
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ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
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IFX_PMU_MODULE_PPE_TC |
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IFX_PMU_MODULE_PPE_EMA |
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IFX_PMU_MODULE_AHBS |
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IFX_PMU_MODULE_DSL_DFE);
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}
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static inline void uninit_pmu(void)
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{
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}
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static inline void reset_ppe(void)
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{
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/*#ifdef MODULE
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// reset PPE
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ifx_rcu_rst(IFX_RCU_DOMAIN_DSLDFE, IFX_RCU_MODULE_PTM);
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udelay(1000);
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ifx_rcu_rst(IFX_RCU_DOMAIN_DSLTC, IFX_RCU_MODULE_PTM);
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udelay(1000);
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ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM);
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udelay(1000);
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*PP32_SRST &= ~0x000303CF;
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udelay(1000);
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*PP32_SRST |= 0x000303CF;
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udelay(1000);
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#endif*/
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}
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static inline void init_pdma(void)
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{
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IFX_REG_W32(0x00000001, PDMA_CFG);
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IFX_REG_W32(0x00082C00, PDMA_RX_CTX_CFG);
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IFX_REG_W32(0x00081B00, PDMA_TX_CTX_CFG);
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IFX_REG_W32(0x02040604, PDMA_RX_MAX_LEN_REG);
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IFX_REG_W32(0x000F003F, PDMA_RX_DELAY_CFG);
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IFX_REG_W32(0x00000011, SAR_MODE_CFG);
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IFX_REG_W32(0x00082A00, SAR_RX_CTX_CFG);
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IFX_REG_W32(0x00082E00, SAR_TX_CTX_CFG);
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IFX_REG_W32(0x00001021, SAR_POLY_CFG_SET0);
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IFX_REG_W32(0x1EDC6F41, SAR_POLY_CFG_SET1);
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IFX_REG_W32(0x04C11DB7, SAR_POLY_CFG_SET2);
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IFX_REG_W32(0x00000F3E, SAR_CRC_SIZE_CFG);
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IFX_REG_W32(0x01001900, SAR_PDMA_RX_CMDBUF_CFG);
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IFX_REG_W32(0x01001A00, SAR_PDMA_TX_CMDBUF_CFG);
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}
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static inline void init_mailbox(void)
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{
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IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
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IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
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IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
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IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
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}
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static inline void init_atm_tc(void)
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{
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IFX_REG_W32(0x00010040, SFSM_CFG0);
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IFX_REG_W32(0x00010040, SFSM_CFG1);
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IFX_REG_W32(0x00020000, SFSM_PGCNT0);
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IFX_REG_W32(0x00020000, SFSM_PGCNT1);
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IFX_REG_W32(0x00000000, DREG_AT_IDLE0);
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IFX_REG_W32(0x00000000, DREG_AT_IDLE1);
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IFX_REG_W32(0x00000000, DREG_AR_IDLE0);
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IFX_REG_W32(0x00000000, DREG_AR_IDLE1);
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IFX_REG_W32(0x0000080C, DREG_B0_LADR);
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IFX_REG_W32(0x0000080C, DREG_B1_LADR);
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IFX_REG_W32(0x000001F0, DREG_AR_CFG0);
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IFX_REG_W32(0x000001F0, DREG_AR_CFG1);
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IFX_REG_W32(0x000001E0, DREG_AT_CFG0);
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IFX_REG_W32(0x000001E0, DREG_AT_CFG1);
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/* clear sync state */
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//IFX_REG_W32(0, SFSM_STATE0);
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//IFX_REG_W32(0, SFSM_STATE1);
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IFX_REG_W32_MASK(0, 1 << 14, SFSM_CFG0); // enable SFSM storing
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IFX_REG_W32_MASK(0, 1 << 14, SFSM_CFG1);
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IFX_REG_W32_MASK(0, 1 << 15, SFSM_CFG0); // HW keep the IDLE cells in RTHA buffer
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IFX_REG_W32_MASK(0, 1 << 15, SFSM_CFG1);
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IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
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IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
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IFX_REG_W32(0x00030028, FFSM_CFG0); // Force_idle
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IFX_REG_W32(0x00030028, FFSM_CFG1);
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}
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static inline void clear_share_buffer(void)
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{
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volatile u32 *p;
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unsigned int i;
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p = SB_RAM0_ADDR(0);
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for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
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IFX_REG_W32(0, p++);
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p = SB_RAM6_ADDR(0);
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for ( i = 0; i < SB_RAM6_DWLEN; i++ )
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IFX_REG_W32(0, p++);
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}
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/*
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* Description:
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* Download PPE firmware binary code.
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* Input:
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* pp32 --- int, which pp32 core
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* src --- u32 *, binary code buffer
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* dword_len --- unsigned int, binary code length in DWORD (32-bit)
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* Output:
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* int --- 0: Success
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* else: Error Code
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*/
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static inline int pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
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{
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unsigned int clr, set;
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volatile u32 *dest;
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if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
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|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
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return -1;
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clr = pp32 ? 0xF0 : 0x0F;
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if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
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set = pp32 ? (3 << 6): (2 << 2);
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else
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set = 0x00;
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IFX_REG_W32_MASK(clr, set, CDM_CFG);
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/* copy code */
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dest = CDM_CODE_MEMORY(pp32, 0);
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while ( code_dword_len-- > 0 )
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IFX_REG_W32(*code_src++, dest++);
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/* copy data */
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dest = CDM_DATA_MEMORY(pp32, 0);
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while ( data_dword_len-- > 0 )
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IFX_REG_W32(*data_src++, dest++);
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return 0;
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}
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/*
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* ####################################
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* Global Function
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* ####################################
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*/
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extern void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor)
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{
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ASSERT(major != NULL, "pointer is NULL");
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ASSERT(minor != NULL, "pointer is NULL");
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*major = FW_VER_ID->major;
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*minor = FW_VER_ID->minor;
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}
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void ifx_ptm_init_chip(void)
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{
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init_pmu();
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reset_ppe();
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init_pdma();
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init_mailbox();
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init_atm_tc();
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clear_share_buffer();
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}
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void ifx_ptm_uninit_chip(void)
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{
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uninit_pmu();
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}
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/*
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* Description:
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* Initialize and start up PP32.
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* Input:
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* none
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* Output:
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* int --- 0: Success
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* else: Error Code
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*/
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int ifx_pp32_start(int pp32)
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{
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unsigned int mask = 1 << (pp32 << 4);
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int ret;
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/* download firmware */
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ret = pp32_download_code(pp32, firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
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if ( ret != 0 )
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return ret;
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/* run PP32 */
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IFX_REG_W32_MASK(mask, 0, PP32_FREEZE);
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/* idle for a while to let PP32 init itself */
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udelay(10);
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return 0;
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}
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/*
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* Description:
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* Halt PP32.
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* Input:
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* none
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* Output:
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* none
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*/
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void ifx_pp32_stop(int pp32)
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{
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unsigned int mask = 1 << (pp32 << 4);
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/* halt PP32 */
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IFX_REG_W32_MASK(0, mask, PP32_FREEZE);
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}
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