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31 lines
1.2 KiB
Diff
31 lines
1.2 KiB
Diff
From 8b88f1e9918c173b24b43015cdb713cdde9e4d17 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Thu, 19 Nov 2020 17:43:14 +0200
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Subject: [PATCH 108/247] clk: at91: sama7g5: decrease lower limit for MCK0
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rate
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On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
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CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
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also changed by DVFS to avoid over/under clocking of MCK0 consumers.
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The lower limit is changed to be able to set MCK0 accordingly by
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DVFS.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/at91/sama7g5.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/clk/at91/sama7g5.c
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+++ b/drivers/clk/at91/sama7g5.c
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@@ -807,7 +807,7 @@ static const struct clk_pll_characterist
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/* MCK0 characteristics. */
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static const struct clk_master_characteristics mck0_characteristics = {
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- .output = { .min = 140000000, .max = 200000000 },
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+ .output = { .min = 50000000, .max = 200000000 },
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.divisors = { 1, 2, 4, 3, 5 },
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.have_div3_pres = 1,
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};
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