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7333c694e3
Update patch with upstream version and automatically refresh with make target/linux/refresh. Also backport one additional fix patch for NAND patch and drop a patch merged upstream. Link: https://github.com/openwrt/openwrt/pull/17725 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
130 lines
4.2 KiB
Diff
130 lines
4.2 KiB
Diff
From 758aa2d7e3c0acfe9c952a1cbe6416ec6130c2a1 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Fri, 3 Jan 2025 15:31:37 +0800
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Subject: [PATCH 2/3] arm64: dts: qcom: ipq9574: Add CMN PLL node
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The CMN PLL clock controller allows selection of an input clock rate
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from a defined set of input clock rates. It in-turn supplies fixed
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rate output clocks to the hardware blocks that provide the ethernet
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functions such as PPE (Packet Process Engine) and connected switch or
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PHY, and to GCC.
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The reference clock of CMN PLL is routed from XO to the CMN PLL through
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the internal WiFi block.
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.XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)-->48 MHZ to CMN PLL.
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The reference input clock from WiFi to CMN PLL is fully controlled by
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the bootstrap pins which select the XO frequency (48 MHZ or 96 MHZ).
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Based on this frequency, the divider in the internal Wi-Fi block is
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automatically configured by hardware (1 for 48 MHZ, 2 for 96 MHZ), to
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ensure output clock to CMN PLL is 48 MHZ.
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-4-c89fb4d4849d@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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.../boot/dts/qcom/ipq9574-rdp-common.dtsi | 17 +++++++++++-
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 ++++++++++++++++++-
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2 files changed, 41 insertions(+), 2 deletions(-)
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
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index 91e104b0f865..bb1ff79360d3 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
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@@ -3,7 +3,7 @@
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* IPQ9574 RDP board common device tree source
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*
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* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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@@ -164,6 +164,21 @@ &usb3 {
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status = "okay";
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};
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+/*
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+ * The bootstrap pins for the board select the XO clock frequency
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+ * (48 MHZ or 96 MHZ used for different RDP type board). This setting
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+ * automatically enables the right dividers, to ensure the reference
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+ * clock output from WiFi to the CMN PLL is 48 MHZ.
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+ */
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+&ref_48mhz_clk {
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+ clock-div = <1>;
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+ clock-mult = <1>;
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+};
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+
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&xo_board_clk {
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clock-frequency = <24000000>;
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};
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+
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+&xo_clk {
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+ clock-frequency = <48000000>;
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+};
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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index 00ee3290c181..c543c3492e93 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -3,10 +3,11 @@
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* IPQ9574 SoC device tree source
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*
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* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,apss-ipq.h>
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+#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
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#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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#include <dt-bindings/interconnect/qcom,ipq9574.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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@@ -19,6 +20,12 @@ / {
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#size-cells = <2>;
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clocks {
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+ ref_48mhz_clk: ref-48mhz-clk {
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+ compatible = "fixed-factor-clock";
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+ clocks = <&xo_clk>;
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+ #clock-cells = <0>;
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+ };
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+
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -28,6 +35,11 @@ xo_board_clk: xo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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+
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+ xo_clk: xo-clk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ };
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};
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cpus {
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@@ -335,6 +347,18 @@ pcie1_phy: phy@fc000 {
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status = "disabled";
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};
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+ cmn_pll: clock-controller@9b000 {
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+ compatible = "qcom,ipq9574-cmn-pll";
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+ reg = <0x0009b000 0x800>;
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+ clocks = <&ref_48mhz_clk>,
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+ <&gcc GCC_CMN_12GPLL_AHB_CLK>,
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+ <&gcc GCC_CMN_12GPLL_SYS_CLK>;
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+ clock-names = "ref", "ahb", "sys";
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+ #clock-cells = <1>;
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+ assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
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+ assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
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+ };
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+
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qfprom: efuse@a4000 {
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compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
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reg = <0x000a4000 0x5a1>;
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--
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2.47.1
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