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c795794eef
Also improves rtl8188eu support. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
193 lines
4.9 KiB
Diff
193 lines
4.9 KiB
Diff
From f1785fbf7c0bc17211c299a647ebc38968a42181 Mon Sep 17 00:00:00 2001
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From: Jes Sorensen <Jes.Sorensen@redhat.com>
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Date: Tue, 13 Sep 2016 15:03:15 -0400
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Subject: [PATCH] rtl8xxxu: Implement 8192e specific power down sequence
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This powers down the 8192e correctly, or at least to the point where
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the firmware will load again, when reloading the driver module.
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Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
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Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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---
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.../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c | 144 ++++++++++++++++++++-
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.../net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 1 +
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2 files changed, 144 insertions(+), 1 deletion(-)
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--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c
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+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c
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@@ -1396,6 +1396,114 @@ exit:
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return ret;
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}
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+static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv)
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+{
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+ struct device *dev = &priv->udev->dev;
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+ u8 val8;
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+ u16 val16;
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+ u32 val32;
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+ int retry, retval;
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+
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+ rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
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+
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+ retry = 100;
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+ retval = -EBUSY;
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+ /*
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+ * Poll 32 bit wide 0x05f8 for 0x00000000 to ensure no TX is pending.
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+ */
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+ do {
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+ val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);
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+ if (!val32) {
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+ retval = 0;
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+ break;
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+ }
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+ } while (retry--);
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+
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+ if (!retry) {
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+ dev_warn(dev, "Failed to flush TX queue\n");
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+ retval = -EBUSY;
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+ goto out;
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+ }
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+
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+ /* Disable CCK and OFDM, clock gated */
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+ val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
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+ val8 &= ~SYS_FUNC_BBRSTB;
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+ rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
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+
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+ udelay(2);
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+
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+ /* Reset whole BB */
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+ val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
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+ val8 &= ~SYS_FUNC_BB_GLB_RSTN;
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+ rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
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+
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+ /* Reset MAC TRX */
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+ val16 = rtl8xxxu_read16(priv, REG_CR);
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+ val16 &= 0xff00;
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+ val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE);
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+ rtl8xxxu_write16(priv, REG_CR, val16);
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+
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+ val16 = rtl8xxxu_read16(priv, REG_CR);
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+ val16 &= ~CR_SECURITY_ENABLE;
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+ rtl8xxxu_write16(priv, REG_CR, val16);
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+
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+ val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
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+ val8 |= DUAL_TSF_TX_OK;
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+ rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
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+
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+out:
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+ return retval;
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+}
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+
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+static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv)
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+{
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+ u8 val8;
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+ int count, ret = 0;
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+
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+ /* Turn off RF */
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+ rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
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+
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+ /* Switch DPDT_SEL_P output from register 0x65[2] */
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+ val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
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+ val8 &= ~LEDCFG2_DPDT_SELECT;
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+ rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
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+
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+ /* 0x0005[1] = 1 turn off MAC by HW state machine*/
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+ val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
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+ val8 |= BIT(1);
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+ rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
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+
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+ for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
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+ val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
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+ if ((val8 & BIT(1)) == 0)
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+ break;
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+ udelay(10);
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+ }
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+
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+ if (!count) {
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+ dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
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+ __func__);
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+ ret = -EBUSY;
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+ goto exit;
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+ }
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+
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+exit:
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+ return ret;
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+}
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+
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+static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv)
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+{
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+ u8 val8;
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+
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+ /* 0x04[12:11] = 01 enable WL suspend */
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+ val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
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+ val8 &= ~(BIT(3) | BIT(4));
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+ val8 |= BIT(3);
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+ rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
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+
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+ return 0;
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+}
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+
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static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
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{
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u16 val16;
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@@ -1446,6 +1554,40 @@ exit:
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return ret;
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}
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+void rtl8192eu_power_off(struct rtl8xxxu_priv *priv)
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+{
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+ u8 val8;
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+ u16 val16;
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+
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+ rtl8xxxu_flush_fifo(priv);
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+
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+ val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
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+ val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
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+ rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
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+
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+ /* Turn off RF */
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+ rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
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+
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+ rtl8192eu_active_to_lps(priv);
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+
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+ /* Reset Firmware if running in RAM */
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+ if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
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+ rtl8xxxu_firmware_self_reset(priv);
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+
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+ /* Reset MCU */
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+ val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
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+ val16 &= ~SYS_FUNC_CPU_ENABLE;
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+ rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
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+
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+ /* Reset MCU ready status */
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+ rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
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+
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+ rtl8xxxu_reset_8051(priv);
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+
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+ rtl8192eu_active_to_emu(priv);
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+ rtl8192eu_emu_to_disabled(priv);
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+}
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+
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static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv)
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{
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u32 val32;
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@@ -1487,7 +1629,7 @@ struct rtl8xxxu_fileops rtl8192eu_fops =
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.parse_efuse = rtl8192eu_parse_efuse,
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.load_firmware = rtl8192eu_load_firmware,
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.power_on = rtl8192eu_power_on,
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- .power_off = rtl8xxxu_power_off,
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+ .power_off = rtl8192eu_power_off,
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.reset_8051 = rtl8xxxu_reset_8051,
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.llt_init = rtl8xxxu_auto_llt_table,
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.init_phy_bb = rtl8192eu_init_phy_bb,
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--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
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+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
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@@ -676,6 +676,7 @@
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#define REG_SCH_TXCMD 0x05d0
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/* define REG_FW_TSF_SYNC_CNT 0x04a0 */
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+#define REG_SCH_TX_CMD 0x05f8
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#define REG_FW_RESET_TSF_CNT_1 0x05fc
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#define REG_FW_RESET_TSF_CNT_0 0x05fd
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#define REG_FW_BCN_DIS_CNT 0x05fe
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