mirror of
https://github.com/openwrt/openwrt.git
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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64)
110 lines
3.2 KiB
Diff
110 lines
3.2 KiB
Diff
From 9f6a310ab3b466940c0a15260987d4cfe868a79a Mon Sep 17 00:00:00 2001
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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Date: Fri, 12 Jun 2020 15:53:52 +0200
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Subject: [PATCH] media: i2c: imx290: Add RAW12 mode support
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Commit c566ac01ceaa02450acc155201772c0623530e76 upstream.
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IMX290 is capable of outputting frames in both Raw Bayer (packed) 10 and
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12 bit formats. Since the driver already supports RAW10 mode, let's add
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the missing RAW12 mode as well.
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Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org>
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Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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---
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drivers/media/i2c/imx290.c | 36 +++++++++++++++++++++++++++++++++---
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1 file changed, 33 insertions(+), 3 deletions(-)
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--- a/drivers/media/i2c/imx290.c
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+++ b/drivers/media/i2c/imx290.c
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@@ -67,6 +67,7 @@ struct imx290 {
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struct clk *xclk;
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struct regmap *regmap;
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u8 nlanes;
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+ u8 bpp;
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struct v4l2_subdev sd;
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struct v4l2_fwnode_endpoint ep;
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@@ -86,10 +87,12 @@ struct imx290 {
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struct imx290_pixfmt {
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u32 code;
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+ u8 bpp;
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};
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static const struct imx290_pixfmt imx290_formats[] = {
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- { MEDIA_BUS_FMT_SRGGB10_1X10 },
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+ { MEDIA_BUS_FMT_SRGGB10_1X10, 10 },
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+ { MEDIA_BUS_FMT_SRGGB12_1X12, 12 },
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};
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static const struct regmap_config imx290_regmap_config = {
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@@ -257,6 +260,18 @@ static const struct imx290_regval imx290
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{ 0x300b, 0x00},
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};
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+static const struct imx290_regval imx290_12bit_settings[] = {
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+ { 0x3005, 0x01 },
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+ { 0x3046, 0x01 },
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+ { 0x3129, 0x00 },
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+ { 0x317c, 0x00 },
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+ { 0x31ec, 0x0e },
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+ { 0x3441, 0x0c },
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+ { 0x3442, 0x0c },
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+ { 0x300a, 0xf0 },
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+ { 0x300b, 0x00 },
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+};
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+
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/* supported link frequencies */
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#define FREQ_INDEX_1080P 0
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#define FREQ_INDEX_720P 1
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@@ -478,7 +493,12 @@ static int imx290_set_ctrl(struct v4l2_c
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} else {
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imx290_write_reg(imx290, IMX290_PGCTRL, 0x00);
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msleep(10);
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- imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW, 0x3c);
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+ if (imx290->bpp == 10)
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+ imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW,
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+ 0x3c);
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+ else /* 12 bits per pixel */
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+ imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW,
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+ 0xf0);
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imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);
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}
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break;
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@@ -550,7 +570,7 @@ static u64 imx290_calc_pixel_rate(struct
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/* pixel rate = link_freq * 2 * nr_of_lanes / bits_per_sample */
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pixel_rate = link_freq * 2 * nlanes;
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- do_div(pixel_rate, 10);
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+ do_div(pixel_rate, imx290->bpp);
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return pixel_rate;
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}
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@@ -587,6 +607,7 @@ static int imx290_set_fmt(struct v4l2_su
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} else {
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format = &imx290->current_format;
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imx290->current_mode = mode;
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+ imx290->bpp = imx290_formats[i].bpp;
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if (imx290->link_freq)
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__v4l2_ctrl_s_ctrl(imx290->link_freq,
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@@ -629,6 +650,15 @@ static int imx290_write_current_format(s
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if (ret < 0) {
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dev_err(imx290->dev, "Could not set format registers\n");
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return ret;
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+ }
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+ break;
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+ case MEDIA_BUS_FMT_SRGGB12_1X12:
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+ ret = imx290_set_register_array(imx290, imx290_12bit_settings,
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+ ARRAY_SIZE(
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+ imx290_12bit_settings));
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+ if (ret < 0) {
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+ dev_err(imx290->dev, "Could not set format registers\n");
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+ return ret;
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}
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break;
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default:
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