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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64)
78 lines
3.1 KiB
Diff
78 lines
3.1 KiB
Diff
From 417e4745f7470ca8b9809056485eb7a81305019b Mon Sep 17 00:00:00 2001
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From: Jim Quinlan <jim2101024@gmail.com>
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Date: Mon, 15 Jan 2018 18:28:39 -0500
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Subject: [PATCH] dt-bindings: pci: Add DT docs for Brcmstb PCIe device
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The DT bindings description of the Brcmstb PCIe device is described. This
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node can be used by almost all Broadcom settop box chips, using
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ARM, ARM64, or MIPS CPU architectures.
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Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
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---
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.../devicetree/bindings/pci/brcmstb-pcie.txt | 59 +++++++++++++++++++
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1 file changed, 59 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
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@@ -0,0 +1,59 @@
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+Brcmstb PCIe Host Controller Device Tree Bindings
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+
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+Required Properties:
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+- compatible
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+ "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs.
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+ "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs.
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+ "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including
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+ the 7278).
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+ "brcm,bcm7278-pcie" -- for 7278 family ARM-based SOCs.
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+
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+- reg -- the register start address and length for the PCIe reg block.
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+- interrupts -- two interrupts are specified; the first interrupt is for
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+ the PCI host controller and the second is for MSI if the built-in
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+ MSI controller is to be used.
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+- interrupt-names -- names of the interrupts (above): "pcie" and "msi".
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+- #address-cells -- set to <3>.
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+- #size-cells -- set to <2>.
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+- #interrupt-cells: set to <1>.
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+- interrupt-map-mask and interrupt-map, standard PCI properties to define the
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+ mapping of the PCIe interface to interrupt numbers.
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+- ranges: ranges for the PCI memory and I/O regions.
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+- linux,pci-domain -- should be unique per host controller.
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+
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+Optional Properties:
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+- clocks -- phandle of pcie clock.
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+- clock-names -- set to "sw_pcie" if clocks is used.
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+- dma-ranges -- Specifies the inbound memory mapping regions when
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+ an "identity map" is not possible.
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+- msi-controller -- this property is typically specified to have the
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+ PCIe controller use its internal MSI controller.
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+- msi-parent -- set to use an external MSI interrupt controller.
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+- brcm,enable-ssc -- (boolean) indicates usage of spread-spectrum clocking.
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+- max-link-speed -- (integer) indicates desired generation of link:
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+ 1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3).
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+
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+Example Node:
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+
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+pcie0: pcie@f0460000 {
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+ reg = <0x0 0xf0460000 0x0 0x9310>;
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+ interrupts = <0x0 0x0 0x4>;
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+ compatible = "brcm,bcm7445-pcie";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000
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+ 0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &intc 0 47 3
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+ 0 0 0 2 &intc 0 48 3
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+ 0 0 0 3 &intc 0 49 3
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+ 0 0 0 4 &intc 0 50 3>;
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+ clocks = <&sw_pcie0>;
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+ clock-names = "sw_pcie";
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+ msi-parent = <&pcie0>; /* use PCIe's internal MSI controller */
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+ msi-controller; /* use PCIe's internal MSI controller */
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+ brcm,ssc;
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+ max-link-speed = <1>;
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+ linux,pci-domain = <0>;
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+ };
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