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91 lines
3.0 KiB
Diff
91 lines
3.0 KiB
Diff
From 9fdab9bd6324314cbdfe96a6da5edef6c29ed5e6 Mon Sep 17 00:00:00 2001
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From: Tim Gover <tim.gover@raspberrypi.org>
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Date: Wed, 9 Jan 2019 14:43:36 +0000
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Subject: [PATCH 549/806] pinctrl-bcm2835: Add support for BCM2838
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GPIO configuration on BCM2838 is largely the same as BCM2835 except for
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the pull up/down configuration. The old mechanism has been replaced
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by new registers which don't require the fixed delay.
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Detect BCN2838 at run-time and use the new mechanism. Backwards
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compatibility for the device-tree configuration has been retained.
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---
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drivers/pinctrl/bcm/pinctrl-bcm2835.c | 58 ++++++++++++++++++++-------
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1 file changed, 44 insertions(+), 14 deletions(-)
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--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
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+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
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@@ -67,6 +67,12 @@
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#define GPPUD 0x94 /* Pin Pull-up/down Enable */
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#define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
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+/* 2711 has a different mechanism for pin pull-up/down/enable */
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+#define GPPUPPDN0 0xe4 /* Pin pull-up/down for pins 15:0 */
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+#define GPPUPPDN1 0xe8 /* Pin pull-up/down for pins 31:16 */
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+#define GPPUPPDN2 0xec /* Pin pull-up/down for pins 47:32 */
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+#define GPPUPPDN3 0xf0 /* Pin pull-up/down for pins 57:48 */
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+
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#define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
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#define FSEL_SHIFT(p) (((p) % 10) * 3)
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#define GPIO_REG_OFFSET(p) ((p) / 32)
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@@ -917,21 +923,45 @@ static void bcm2835_pull_config_set(stru
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unsigned int pin, unsigned int arg)
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{
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u32 off, bit;
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+ /* BCM2835, BCM2836 & BCM2837 return 'gpio' for this unused register */
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+ int is_2835 = bcm2835_gpio_rd(pc, GPPUPPDN3) == 0x6770696f;
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- off = GPIO_REG_OFFSET(pin);
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- bit = GPIO_REG_SHIFT(pin);
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-
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- bcm2835_gpio_wr(pc, GPPUD, arg & 3);
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- /*
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- * BCM2835 datasheet say to wait 150 cycles, but not of what.
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- * But the VideoCore firmware delay for this operation
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- * based nearly on the same amount of VPU cycles and this clock
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- * runs at 250 MHz.
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- */
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- udelay(1);
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- bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
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- udelay(1);
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- bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
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+ if (is_2835) {
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+ off = GPIO_REG_OFFSET(pin);
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+ bit = GPIO_REG_SHIFT(pin);
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+ /*
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+ * BCM2835 datasheet say to wait 150 cycles, but not of what.
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+ * But the VideoCore firmware delay for this operation
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+ * based nearly on the same amount of VPU cycles and this clock
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+ * runs at 250 MHz.
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+ */
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+ bcm2835_gpio_wr(pc, GPPUD, arg & 3);
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+ udelay(1);
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+ bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
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+ udelay(1);
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+ bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
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+ } else {
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+ u32 reg;
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+ int lsb;
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+
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+ off = (pin >> 4);
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+ if (off > 3)
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+ return;
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+ lsb = (pin & 0xf) << 1;
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+
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+ /* The up/down semantics are reversed compared to BCM2835.
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+ * Instead of updating all the device tree files, translate the
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+ * values here.
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+ */
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+ if (arg == 2)
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+ arg = 1;
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+ else if (arg == 1)
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+ arg = 2;
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+ reg = bcm2835_gpio_rd(pc, GPPUPPDN0 + (off *4));
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+ reg &= ~(0x3 << lsb);
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+ reg |= (arg & 3) << lsb;
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+ bcm2835_gpio_wr(pc, GPPUPPDN0 + (off * 4), reg);
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+ }
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}
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static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
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