mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 06:57:57 +00:00
7a1815f64d
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.59
Removed upstreamed:
- generic/backport-6.6/777-netfilter-xtables-fix-typo-causing-some-targets-to-not-load-on-IPv6.patch[1]
- generic/backport-6.6/780-24-v6.12-r8169-avoid-unsolicited-interrupts.patch[2]
All other patches automatically rebased.
1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.59&id=433742ba96baf30c21e654ce3e698ad87100593b
2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.59&id=7d6d46b429804b1a182106e27e2f8c0e84689e1a
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/16835
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 4fc47c6000)
92 lines
2.7 KiB
Diff
92 lines
2.7 KiB
Diff
From 97789b93b792fc97ad4476b79e0f38ffa8e7e0ee Mon Sep 17 00:00:00 2001
|
|
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
|
Date: Fri, 20 Oct 2023 16:11:41 +0200
|
|
Subject: [PATCH] usb: dwc3: add optional PHY interface clocks
|
|
|
|
On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
|
|
requires two extra clocks to be enabled. Without these extra clocks
|
|
hot-plugging USB devices is broken.
|
|
|
|
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
|
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
|
|
Link: https://lore.kernel.org/r/20231020150022.48725-3-sebastian.reichel@collabora.com
|
|
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
---
|
|
drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++
|
|
drivers/usb/dwc3/core.h | 4 ++++
|
|
2 files changed, 32 insertions(+)
|
|
|
|
--- a/drivers/usb/dwc3/core.c
|
|
+++ b/drivers/usb/dwc3/core.c
|
|
@@ -845,8 +845,20 @@ static int dwc3_clk_enable(struct dwc3 *
|
|
if (ret)
|
|
goto disable_ref_clk;
|
|
|
|
+ ret = clk_prepare_enable(dwc->utmi_clk);
|
|
+ if (ret)
|
|
+ goto disable_susp_clk;
|
|
+
|
|
+ ret = clk_prepare_enable(dwc->pipe_clk);
|
|
+ if (ret)
|
|
+ goto disable_utmi_clk;
|
|
+
|
|
return 0;
|
|
|
|
+disable_utmi_clk:
|
|
+ clk_disable_unprepare(dwc->utmi_clk);
|
|
+disable_susp_clk:
|
|
+ clk_disable_unprepare(dwc->susp_clk);
|
|
disable_ref_clk:
|
|
clk_disable_unprepare(dwc->ref_clk);
|
|
disable_bus_clk:
|
|
@@ -856,6 +868,8 @@ disable_bus_clk:
|
|
|
|
static void dwc3_clk_disable(struct dwc3 *dwc)
|
|
{
|
|
+ clk_disable_unprepare(dwc->pipe_clk);
|
|
+ clk_disable_unprepare(dwc->utmi_clk);
|
|
clk_disable_unprepare(dwc->susp_clk);
|
|
clk_disable_unprepare(dwc->ref_clk);
|
|
clk_disable_unprepare(dwc->bus_clk);
|
|
@@ -1884,6 +1898,20 @@ static int dwc3_get_clocks(struct dwc3 *
|
|
}
|
|
}
|
|
|
|
+ /* specific to Rockchip RK3588 */
|
|
+ dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
|
|
+ if (IS_ERR(dwc->utmi_clk)) {
|
|
+ return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
|
|
+ "could not get utmi clock\n");
|
|
+ }
|
|
+
|
|
+ /* specific to Rockchip RK3588 */
|
|
+ dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
|
|
+ if (IS_ERR(dwc->pipe_clk)) {
|
|
+ return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
|
|
+ "could not get pipe clock\n");
|
|
+ }
|
|
+
|
|
return 0;
|
|
}
|
|
|
|
--- a/drivers/usb/dwc3/core.h
|
|
+++ b/drivers/usb/dwc3/core.h
|
|
@@ -997,6 +997,8 @@ struct dwc3_scratchpad_array {
|
|
* @bus_clk: clock for accessing the registers
|
|
* @ref_clk: reference clock
|
|
* @susp_clk: clock used when the SS phy is in low power (S3) state
|
|
+ * @utmi_clk: clock used for USB2 PHY communication
|
|
+ * @pipe_clk: clock used for USB3 PHY communication
|
|
* @reset: reset control
|
|
* @regs: base address for our registers
|
|
* @regs_size: address space size
|
|
@@ -1169,6 +1171,8 @@ struct dwc3 {
|
|
struct clk *bus_clk;
|
|
struct clk *ref_clk;
|
|
struct clk *susp_clk;
|
|
+ struct clk *utmi_clk;
|
|
+ struct clk *pipe_clk;
|
|
|
|
struct reset_control *reset;
|
|
|