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05ed7dc50d
Patches automatically rebased. Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
37 lines
1.1 KiB
Diff
37 lines
1.1 KiB
Diff
From cf96a88e44f1fde9f1a30ab335329ff9e895e6f8 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Mon, 23 Aug 2021 16:19:13 +0300
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Subject: [PATCH 224/247] ARM: dts: at91: sama7g5: add ram controllers
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Add RAM and RAMC PHY controllers. These are necessary for platform
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specific power management code.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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Link: https://lore.kernel.org/r/20210823131915.23857-3-claudiu.beznea@microchip.com
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---
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arch/arm/boot/dts/sama7g5.dtsi | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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--- a/arch/arm/boot/dts/sama7g5.dtsi
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+++ b/arch/arm/boot/dts/sama7g5.dtsi
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@@ -515,6 +515,18 @@
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};
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};
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+ uddrc: uddrc@e3800000 {
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+ compatible = "microchip,sama7g5-uddrc";
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+ reg = <0xe3800000 0x4000>;
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+ status = "okay";
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+ };
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+
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+ ddr3phy: ddr3phy@e3804000 {
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+ compatible = "microchip,sama7g5-ddr3phy";
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+ reg = <0xe3804000 0x1000>;
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+ status = "okay";
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+ };
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+
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gic: interrupt-controller@e8c11000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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