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d6a9a92e32
Seemingly unneeded based on new upstream code so manually deleted: layerscape: 820-usb-0007-usb-dwc3-gadget-increase-timeout-value-for-send-ep-c.patch Manually merged: generic-hack: 251-sound_kconfig.patch All other modifications made by update_kernel.sh Build system: x86_64 Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711 Run-tested: ipq806x/R7800, lantiq/Easybox 904 xDSL No dmesg regressions, everything functional Signed-off-by: John Audia <graysky@archlinux.us> [add lantiq test report, minor commit message clarification] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
90 lines
3.0 KiB
Diff
90 lines
3.0 KiB
Diff
From 32e84f4f525e2a0d7dc021b5795df34407096b0e Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Thu, 7 May 2020 18:16:08 +0100
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Subject: [PATCH] vc4_hdmi: Adjust CEC ref clock based on its input
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clock
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2711 uses a fixed 27MHz input, earlier models use the HSM clock
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 11 ++++++++---
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drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++
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2 files changed, 11 insertions(+), 3 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -79,6 +79,7 @@
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# define VC4_HD_M_ENABLE BIT(0)
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#define CEC_CLOCK_FREQ 40000
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+#define VC4_HSM_CLOCK 163682864
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static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
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{
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@@ -755,8 +756,7 @@ static u32 vc4_hdmi_calc_hsm_clock(struc
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* needs to be a bit higher than the pixel clock rate
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* (generally 148.5Mhz).
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*/
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-
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- return 163682864;
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+ return VC4_HSM_CLOCK;
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}
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static u32 vc5_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate)
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@@ -1400,6 +1400,7 @@ static int vc4_hdmi_cec_init(struct vc4_
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struct cec_connector_info conn_info;
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struct platform_device *pdev = vc4_hdmi->pdev;
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u32 value;
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+ u32 clk_cnt;
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int ret;
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if (!vc4_hdmi->variant->cec_available)
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@@ -1424,8 +1425,9 @@ static int vc4_hdmi_cec_init(struct vc4_
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* divider: the hsm_clock rate and this divider setting will
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* give a 40 kHz CEC clock.
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*/
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+ clk_cnt = vc4_hdmi->variant->cec_input_clock / CEC_CLOCK_FREQ;
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value |= VC4_HDMI_CEC_ADDR_MASK |
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- (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
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+ ((clk_cnt-1) << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
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HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
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ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
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vc4_cec_irq_handler,
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@@ -1770,6 +1772,7 @@ static int vc4_hdmi_dev_remove(struct pl
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static const struct vc4_hdmi_variant bcm2835_variant = {
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.max_pixel_clock = 162000000,
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+ .cec_input_clock = VC4_HSM_CLOCK,
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.audio_available = true,
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.cec_available = true,
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.registers = vc4_hdmi_fields,
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@@ -1794,6 +1797,7 @@ static const struct vc4_hdmi_variant bcm
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.id = 0,
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.audio_available = true,
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.max_pixel_clock = 297000000,
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+ .cec_input_clock = 27000000,
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.registers = vc5_hdmi_hdmi0_fields,
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.num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
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.phy_lane_mapping = {
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@@ -1821,6 +1825,7 @@ static const struct vc4_hdmi_variant bcm
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.id = 1,
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.audio_available = true,
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.max_pixel_clock = 297000000,
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+ .cec_input_clock = 27000000,
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.registers = vc5_hdmi_hdmi1_fields,
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.num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
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.phy_lane_mapping = {
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
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@@ -48,6 +48,9 @@ struct vc4_hdmi_variant {
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/* Maximum pixel clock supported by the controller (in Hz) */
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unsigned long long max_pixel_clock;
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+ /* Input clock frequency of CEC block (in Hz) */
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+ unsigned long cec_input_clock;
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+
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/* List of the registers available on that variant */
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const struct vc4_hdmi_register *registers;
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