mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 14:13:16 +00:00
b4c02c9998
Removed upstreamed patches:
generic/pending-5.4
445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch
446-mtd-spinand-gigadevice-Add-QE-Bit.patch
pistachio/patches-5.4
150-pwm-img-Fix-null-pointer-access-in-probe.patch
Manually rebased:
layerscape/patches-5.4
801-audio-0011-Revert-ASoC-fsl_sai-add-of_match-data.patch
801-audio-0039-MLK-16224-6-ASoC-fsl_sai-fix-DSD-suspend-resume.patch
801-audio-0073-MLK-21957-3-ASoC-fsl_sai-add-bitcount-and-timestamp-.patch
820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
mvebu (mamba, rango), x86_64, ramips/mt7621
Run-tested: ipq806x/R7800, mvebu (mamba, rango), x86_64, ramips (RT-AC57U)
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[alter 820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
59 lines
1.6 KiB
Diff
59 lines
1.6 KiB
Diff
From 6c37f43308f29a59bc67d4ed010f8fbbf076ec79 Mon Sep 17 00:00:00 2001
|
|
From: popcornmix <popcornmix@gmail.com>
|
|
Date: Tue, 3 Sep 2019 20:28:00 +0100
|
|
Subject: [PATCH] clk-bcm2835: Disable v3d clock
|
|
|
|
This is controlled by firmware, see clk-raspberrypi.c
|
|
|
|
Signed-off-by: popcornmix <popcornmix@gmail.com>
|
|
---
|
|
drivers/clk/bcm/clk-bcm2835.c | 30 ++++++++++++------------------
|
|
1 file changed, 12 insertions(+), 18 deletions(-)
|
|
|
|
--- a/drivers/clk/bcm/clk-bcm2835.c
|
|
+++ b/drivers/clk/bcm/clk-bcm2835.c
|
|
@@ -1734,16 +1734,12 @@ static const struct bcm2835_clk_desc clk
|
|
.hold_mask = CM_PLLA_HOLDCORE,
|
|
.fixed_divider = 1,
|
|
.flags = CLK_SET_RATE_PARENT),
|
|
- [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
|
|
- SOC_ALL,
|
|
- .name = "plla_per",
|
|
- .source_pll = "plla",
|
|
- .cm_reg = CM_PLLA,
|
|
- .a2w_reg = A2W_PLLA_PER,
|
|
- .load_mask = CM_PLLA_LOADPER,
|
|
- .hold_mask = CM_PLLA_HOLDPER,
|
|
- .fixed_divider = 1,
|
|
- .flags = CLK_SET_RATE_PARENT),
|
|
+
|
|
+ /*
|
|
+ * PLLA_PER is used for gpu clocks. Controlled by firmware, see
|
|
+ * clk-raspberrypi.c.
|
|
+ */
|
|
+
|
|
[BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
|
|
SOC_ALL,
|
|
.name = "plla_dsi0",
|
|
@@ -2021,14 +2017,12 @@ static const struct bcm2835_clk_desc clk
|
|
.int_bits = 6,
|
|
.frac_bits = 0,
|
|
.tcnt_mux = 3),
|
|
- [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
|
|
- SOC_ALL,
|
|
- .name = "v3d",
|
|
- .ctl_reg = CM_V3DCTL,
|
|
- .div_reg = CM_V3DDIV,
|
|
- .int_bits = 4,
|
|
- .frac_bits = 8,
|
|
- .tcnt_mux = 4),
|
|
+
|
|
+ /*
|
|
+ * CLOCK_V3D is used for v3d clock. Controlled by firmware, see
|
|
+ * clk-raspberrypi.c.
|
|
+ */
|
|
+
|
|
/*
|
|
* VPU clock. This doesn't have an enable bit, since it drives
|
|
* the bus for everything else, and is special so it doesn't need
|