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54 lines
2.0 KiB
Diff
54 lines
2.0 KiB
Diff
From eff78bc2c385f592294278582f38ad5fa4ed2b34 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Date: Wed, 27 Jan 2016 08:47:03 +0100
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Subject: [PATCH] mtd: brcmnand: set initial ECC params based on info from HW
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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So far we were depending on nand_dt_init getting ECC info from DT and
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setting it in ECC struct. It is possible to simply read this info from
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hardware registers which makes adding support for new hardware way
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easier (no more guessing & trying all combinations).
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Please note it still gives a precedence to DT which was overwrite
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whatever was initially set by the driver.
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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---
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It took me hours to figure out how to setup NAND on my D-Link DIR-885L.
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This should be very helpful for ppl adding new devices support.
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---
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drivers/mtd/nand/brcmnand/brcmnand.c | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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--- a/drivers/mtd/nand/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/brcmnand/brcmnand.c
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@@ -645,6 +645,17 @@ static inline u32 brcmnand_ecc_level_mas
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return mask << NAND_ACC_CONTROL_ECC_SHIFT;
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}
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+static int brcmnand_get_ecc_strength(struct brcmnand_host *host)
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+{
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+ struct brcmnand_controller *ctrl = host->ctrl;
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+ u32 mask = brcmnand_ecc_level_mask(ctrl);
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+ u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
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+ BRCMNAND_CS_ACC_CONTROL);
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+
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+ return (nand_readreg(ctrl, acc_control_offs) & mask) >>
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+ NAND_ACC_CONTROL_ECC_SHIFT;
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+}
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+
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static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
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{
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struct brcmnand_controller *ctrl = host->ctrl;
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@@ -1997,6 +2008,9 @@ static int brcmnand_init_cs(struct brcmn
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nand_writereg(ctrl, cfg_offs,
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nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
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+ chip->ecc.strength = brcmnand_get_ecc_strength(host);
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+ chip->ecc.size = brcmnand_get_sector_size_1k(host) ? 1024 : 512;
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+
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if (nand_scan_ident(mtd, 1, NULL))
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return -ENXIO;
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