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7774b86019
Add the missing pinctrl properties on the ethernet node. GMAC1 will start working with this change. Link: https://lore.kernel.org/netdev/83a35aa3-6cb8-2bc4-2ff4-64278bbcd8c8@arinc9.com/ Overwrite pinctrl-0 property without rgmii2_pins on devicetrees which use the rgmii2 pins as GPIO (22 - 33). Give gpio function to rgmii2 pin group on mt7621_tplink_archer-x6-v3.dtsi which uses GPIO 28. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
237 lines
3.6 KiB
Plaintext
237 lines
3.6 KiB
Plaintext
#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "d-team,pbr-m1", "mediatek,mt7621-soc";
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model = "PBR-M1";
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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leds {
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compatible = "gpio-leds";
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power {
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label = "blue:power";
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gpios = <&gpio 31 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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led_sys: sys {
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label = "blue:sys";
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gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
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};
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internet {
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label = "blue:internet";
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gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
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};
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wlan2g {
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label = "blue:wlan2g";
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gpios = <&gpio 33 GPIO_ACTIVE_LOW>;
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};
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wlan5g {
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label = "blue:wlan5g";
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gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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gpio_export {
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compatible = "gpio-export";
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#size-cells = <0>;
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power_usb2 {
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gpio-export,name = "power_usb2";
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gpio-export,output = <1>;
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gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
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};
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power_usb3 {
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gpio-export,name = "power_usb3";
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gpio-export,output = <1>;
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gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
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};
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power_sata {
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gpio-export,name = "power_sata";
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gpio-export,output = <1>;
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gpios = <&gpio 27 GPIO_ACTIVE_HIGH>;
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};
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};
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beeper: beeper {
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compatible = "gpio-beeper";
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gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
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};
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};
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&i2c {
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status = "okay";
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rtc@51 {
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status = "okay";
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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};
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&sdhci {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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broken-flash-reset;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x50000 0x1fb0000>;
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};
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};
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};
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};
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&pinctrl {
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uart3_gpio: uart3-gpio {
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uart3 {
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groups = "uart3";
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function = "gpio";
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};
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};
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};
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&pcie {
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status = "okay";
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pinctrl-0 = <&pcie_pins>, <&uart3_gpio>;
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reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
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<&gpio 7 GPIO_ACTIVE_LOW>;
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};
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&pcie0 {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&pcie1 {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x0000>;
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};
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};
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ðernet {
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pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;
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};
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&gmac0 {
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nvmem-cells = <&macaddr_factory_e000>;
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nvmem-cell-names = "mac-address";
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};
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&switch0 {
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ports {
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port@0 {
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status = "okay";
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label = "lan1";
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};
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port@1 {
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status = "okay";
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label = "lan2";
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};
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port@2 {
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status = "okay";
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label = "lan3";
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};
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port@3 {
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status = "okay";
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label = "lan4";
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};
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port@4 {
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status = "okay";
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label = "wan";
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nvmem-cells = <&macaddr_factory_e006>;
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nvmem-cell-names = "mac-address";
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};
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};
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};
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&state_default {
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gpio {
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groups = "wdt", "rgmii2", "jtag";
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function = "gpio";
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};
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};
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&factory {
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_factory_e000: macaddr@e000 {
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reg = <0xe000 0x6>;
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};
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macaddr_factory_e006: macaddr@e006 {
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reg = <0xe006 0x6>;
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};
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};
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