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201d3d1a82
- Former "mir3g" board name becomes "xiaomi,mir3g". - Reorder some entries to maintain alphabetical order. - Change DTS so status LEDs (yellow/red/blue) mimic Xiaomi stock firmware: (Section Indicator) <http://files.xiaomi-mi.co.uk/files/router_pro/router%20PRO%20EN.pdf> <http://files.xiaomi-mi.co.uk/files/Mi_WiFi_router_3/MiWiFi_router3_EN.pdf> |Yellow: Update (LED flickering), the launch of the system (steady light); |Blue: during normal operation (steady light); |Red: Safe mode (display flicker), system failure (steady light); Signed-off-by: Ozgur Can Leonard <ozgurcan@gmail.com> [Added link to similar Router 3 model] Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
208 lines
4.0 KiB
Plaintext
208 lines
4.0 KiB
Plaintext
/dts-v1/;
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "xiaomi,mir3g", "mediatek,mt7621-soc";
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model = "Xiaomi Mi Router 3G";
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aliases {
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led-boot = &led_status_yellow;
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led-failsafe = &led_status_red;
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led-running = &led_status_blue;
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led-upgrade = &led_status_yellow;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200n8";
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};
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leds {
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compatible = "gpio-leds";
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led_status_red: status_red {
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label = "mir3g:red:status";
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gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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};
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led_status_blue: status_blue {
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label = "mir3g:blue:status";
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gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
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};
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led_status_yellow: status_yellow {
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label = "mir3g:yellow:status";
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gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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};
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wan_amber {
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label = "mir3g:amber:wan";
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gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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};
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lan1_amber {
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label = "mir3g:amber:lan1";
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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lan2_amber {
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label = "mir3g:amber:lan2";
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gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
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};
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};
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button {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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reg_usb_vbus: regulator {
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compatible = "regulator-fixed";
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regulator-name = "usb_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&xhci {
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vbus-supply = <®_usb_vbus>;
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};
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&nand {
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Bootloader";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "Config";
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reg = <0x80000 0x40000>;
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};
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partition@c0000 {
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label = "Bdata";
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reg = <0xc0000 0x40000>;
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read-only;
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};
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factory: partition@100000 {
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label = "Factory";
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reg = <0x100000 0x40000>;
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read-only;
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};
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partition@140000 {
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label = "crash";
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reg = <0x140000 0x40000>;
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};
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partition@180000 {
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label = "crash_syslog";
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reg = <0x180000 0x40000>;
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};
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partition@1c0000 {
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label = "reserved0";
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reg = <0x1c0000 0x40000>;
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read-only;
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};
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/* uboot expects to find kernels at 0x200000 & 0x600000
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* referred to as system 1 & system 2 respectively.
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* a kernel is considered suitable for handing control over
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* if its linux magic number exists & uImage CRC are correct.
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* If either of those conditions fail, a matching sys'n'_fail flag
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* is set in uboot env & a restart performed in the hope that the
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* alternate kernel is okay.
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* if neither kernel checksums ok and both are marked failed, system 2
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* is booted anyway.
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*
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* Note uboot's tftp flash install writes the transferred
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* image to both kernel partitions.
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*/
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partition@200000 {
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label = "kernel_stock";
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reg = <0x200000 0x400000>;
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};
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partition@600000 {
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label = "kernel";
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reg = <0x600000 0x400000>;
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};
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/* ubi partition is the result of squashing
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* next consecutive stock partitions:
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* - rootfs0 (rootfs partition for stock kernel0),
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* - rootfs1 (rootfs partition for stock failsafe kernel1),
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* - overlay (used as ubi overlay in stock fw)
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* resulting 117,5MiB space for packages.
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*/
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partition@a00000 {
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label = "ubi";
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reg = <0xa00000 0x7580000>;
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};
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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compatible = "pci14c3,7603";
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x0000>;
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ieee80211-freq-limit = <2400000 2500000>;
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};
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};
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&pcie1 {
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wifi@0,0 {
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compatible = "pci14c3,7662";
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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ðernet {
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mtd-mac-address = <&factory 0xe000>;
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mediatek,portmap = "lwlll";
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "jtag", "uart2", "uart3", "wdt";
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ralink,function = "gpio";
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};
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};
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};
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