mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-30 18:47:06 +00:00
4f74957584
This adds the patches to get fairly complete Gemini support
using kernel v4.14. It is mainly a backport of patches from
kernel v4.16 with omissions of things like graphics that require
substantial changes and will be better handled once we move
to the v4.16 kernel proper.
On top of this are some WIP patches for USB support.
Tested on Raidsonic NAS4220B and D-link DNS-313.
ChangeLog v4->v5:
- Fix ethernet single gmac usecase
- Fix USB reset (patch from Hans)
- Fix Raidsonic ethernet skew delay
- Fix kernel config (bridge, squashfs, jffs2, usb)
- Disable second usb port on Raidsonic board until fotg210_hcd is fixed
ChangeLog v3->v4:
- Make sure to use tabs rather than spaces in base-files.
- Use the dns313 image tool from the firmware-utils.
- Break out the addition of the v4.14 patches and the removal
of the v4.4 patches to separate (big) patches.
ChangeLog v2->v3:
- Update the kernel config as indicated by Hauke Martens:
- Regenerate again after rebasing using kernel_oldconfig
dropping a few optimization settings that are now generic
- Drop CFG80211 stuff (module)
- Drop CIFS stuff (module)
- Drop MAC80211 (module)
- Drop wireless drivers (module)
- Enabled OverlayFS
- Added proper DNS-313 boot image generation with the special
file header tool.
- Disable CMA in the kernel
- Enable LZMA compression of the kernel
- Consequently name the nas4220b images nas4220b
- Update preinit MAC detection script to handle also DNS-313
- Add board.d/03_hdparm to set the disk to spin down after
1 minute by default, if we have the hdparm tool installed
ChangeLog v1->v2:
- Processed config through kernel_oldconfig
- Processed patches through make target/linux/{clean,refresh} V=99
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Roman Yeryomin <roman@advem.lv>
187 lines
7.0 KiB
Diff
187 lines
7.0 KiB
Diff
From e7759c44e0c20dd6b5a259300acdc7350ea6dd32 Mon Sep 17 00:00:00 2001
|
|
From: Linus Walleij <linus.walleij@linaro.org>
|
|
Date: Mon, 6 Nov 2017 21:27:34 +0100
|
|
Subject: [PATCH 07/31] pinctrl: gemini: Fix GMAC groups
|
|
|
|
The GMII groups need to be split across GMAC0 and GMAC1 since
|
|
GMAC0 is always available but GMAC1 masks GPIO2 lines 0-7
|
|
so we might want just one interface out.
|
|
|
|
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
---
|
|
drivers/pinctrl/pinctrl-gemini.c | 79 +++++++++++++++++++++++++++-------------
|
|
1 file changed, 54 insertions(+), 25 deletions(-)
|
|
|
|
--- a/drivers/pinctrl/pinctrl-gemini.c
|
|
+++ b/drivers/pinctrl/pinctrl-gemini.c
|
|
@@ -96,6 +96,13 @@ struct gemini_pin_group {
|
|
* you are stuck with it.
|
|
*/
|
|
#define GLOBAL_MISC_CTRL 0x30
|
|
+#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27)
|
|
+/* Not really used */
|
|
+#define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28)
|
|
+/* Activated with GMAC1 */
|
|
+#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27)
|
|
+/* This will be the default */
|
|
+#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0
|
|
#define TVC_CLK_PAD_ENABLE BIT(20)
|
|
#define PCI_CLK_PAD_ENABLE BIT(17)
|
|
#define LPC_CLK_PAD_ENABLE BIT(16)
|
|
@@ -109,8 +116,8 @@ struct gemini_pin_group {
|
|
#define NAND_PADS_DISABLE BIT(2)
|
|
#define PFLASH_PADS_DISABLE BIT(1)
|
|
#define SFLASH_PADS_DISABLE BIT(0)
|
|
-#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20))
|
|
-#define PADS_MAXBIT 20
|
|
+#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))
|
|
+#define PADS_MAXBIT 27
|
|
|
|
/* Ordered by bit index */
|
|
static const char * const gemini_padgroups[] = {
|
|
@@ -516,9 +523,12 @@ static const unsigned int usb_3512_pins[
|
|
};
|
|
|
|
/* GMII, ethernet pins */
|
|
-static const unsigned int gmii_3512_pins[] = {
|
|
- 311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296,
|
|
- 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281
|
|
+static const unsigned int gmii_gmac0_3512_pins[] = {
|
|
+ 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313
|
|
+};
|
|
+
|
|
+static const unsigned int gmii_gmac1_3512_pins[] = {
|
|
+ 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317
|
|
};
|
|
|
|
static const unsigned int pci_3512_pins[] = {
|
|
@@ -668,10 +678,10 @@ static const unsigned int gpio1c_3512_pi
|
|
/* The GPIO1D (28-31) pins overlap with LCD and TVC */
|
|
static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
|
|
|
|
-/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */
|
|
+/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
|
|
static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
|
|
|
|
-/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */
|
|
+/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
|
|
static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
|
|
|
|
/* The GPIO2C (8-31) pins overlap with PCI */
|
|
@@ -738,9 +748,16 @@ static const struct gemini_pin_group gem
|
|
.num_pins = ARRAY_SIZE(usb_3512_pins),
|
|
},
|
|
{
|
|
- .name = "gmiigrp",
|
|
- .pins = gmii_3512_pins,
|
|
- .num_pins = ARRAY_SIZE(gmii_3512_pins),
|
|
+ .name = "gmii_gmac0_grp",
|
|
+ .pins = gmii_gmac0_3512_pins,
|
|
+ .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
|
|
+ },
|
|
+ {
|
|
+ .name = "gmii_gmac1_grp",
|
|
+ .pins = gmii_gmac1_3512_pins,
|
|
+ .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
|
|
+ /* Bring out RGMII on the GMAC1 pins */
|
|
+ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
|
|
},
|
|
{
|
|
.name = "pcigrp",
|
|
@@ -954,14 +971,15 @@ static const struct gemini_pin_group gem
|
|
.name = "gpio2agrp",
|
|
.pins = gpio2a_3512_pins,
|
|
.num_pins = ARRAY_SIZE(gpio2a_3512_pins),
|
|
- /* Conflict with GMII and extended parallel flash */
|
|
+ .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
|
|
+ /* Conflict with GMII GMAC1 and extended parallel flash */
|
|
},
|
|
{
|
|
.name = "gpio2bgrp",
|
|
.pins = gpio2b_3512_pins,
|
|
.num_pins = ARRAY_SIZE(gpio2b_3512_pins),
|
|
- /* Conflict with GMII, extended parallel flash and LCD */
|
|
- .mask = LCD_PADS_ENABLE,
|
|
+ /* Conflict with GMII GMAC1, extended parallel flash and LCD */
|
|
+ .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
|
|
},
|
|
{
|
|
.name = "gpio2cgrp",
|
|
@@ -1441,9 +1459,12 @@ static const unsigned int usb_3516_pins[
|
|
};
|
|
|
|
/* GMII, ethernet pins */
|
|
-static const unsigned int gmii_3516_pins[] = {
|
|
- 306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347,
|
|
- 348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391
|
|
+static const unsigned int gmii_gmac0_3516_pins[] = {
|
|
+ 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387
|
|
+};
|
|
+
|
|
+static const unsigned int gmii_gmac1_3516_pins[] = {
|
|
+ 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391
|
|
};
|
|
|
|
static const unsigned int pci_3516_pins[] = {
|
|
@@ -1585,10 +1606,10 @@ static const unsigned int gpio1c_3516_pi
|
|
/* The GPIO1D (28-31) pins overlap with TVC */
|
|
static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 };
|
|
|
|
-/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */
|
|
+/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
|
|
static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 };
|
|
|
|
-/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */
|
|
+/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
|
|
static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 };
|
|
|
|
/* The GPIO2C (8-31) pins overlap with PCI */
|
|
@@ -1660,9 +1681,16 @@ static const struct gemini_pin_group gem
|
|
.num_pins = ARRAY_SIZE(usb_3516_pins),
|
|
},
|
|
{
|
|
- .name = "gmiigrp",
|
|
- .pins = gmii_3516_pins,
|
|
- .num_pins = ARRAY_SIZE(gmii_3516_pins),
|
|
+ .name = "gmii_gmac0_grp",
|
|
+ .pins = gmii_gmac0_3516_pins,
|
|
+ .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
|
|
+ },
|
|
+ {
|
|
+ .name = "gmii_gmac1_grp",
|
|
+ .pins = gmii_gmac1_3516_pins,
|
|
+ .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
|
|
+ /* Bring out RGMII on the GMAC1 pins */
|
|
+ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
|
|
},
|
|
{
|
|
.name = "pcigrp",
|
|
@@ -1861,14 +1889,15 @@ static const struct gemini_pin_group gem
|
|
.name = "gpio2agrp",
|
|
.pins = gpio2a_3516_pins,
|
|
.num_pins = ARRAY_SIZE(gpio2a_3516_pins),
|
|
- /* Conflict with GMII and extended parallel flash */
|
|
+ .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
|
|
+ /* Conflict with GMII GMAC1 and extended parallel flash */
|
|
},
|
|
{
|
|
.name = "gpio2bgrp",
|
|
.pins = gpio2b_3516_pins,
|
|
.num_pins = ARRAY_SIZE(gpio2b_3516_pins),
|
|
- /* Conflict with GMII, extended parallel flash and LCD */
|
|
- .mask = LCD_PADS_ENABLE,
|
|
+ /* Conflict with GMII GMAC1, extended parallel flash and LCD */
|
|
+ .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
|
|
},
|
|
{
|
|
.name = "gpio2cgrp",
|
|
@@ -1971,7 +2000,7 @@ static const char * const icegrps[] = {
|
|
static const char * const idegrps[] = { "idegrp" };
|
|
static const char * const satagrps[] = { "satagrp" };
|
|
static const char * const usbgrps[] = { "usbgrp" };
|
|
-static const char * const gmiigrps[] = { "gmiigrp" };
|
|
+static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" };
|
|
static const char * const pcigrps[] = { "pcigrp" };
|
|
static const char * const lpcgrps[] = { "lpcgrp" };
|
|
static const char * const lcdgrps[] = { "lcdgrp" };
|