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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
60 lines
2.0 KiB
Diff
60 lines
2.0 KiB
Diff
From 813ba3e427671ba3ff35c825087b03f0ad91cf02 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Mon, 7 Nov 2022 14:28:59 +0100
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Subject: [PATCH] clk: qcom: reset: support resetting multiple bits
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This patch adds the support for giving the complete bitmask
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in reset structure and reset operation will use this bitmask
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for all reset operations.
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Currently, reset structure only takes a single bit for each reset
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and then calculates the bitmask by using the BIT() macro.
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However, this is not sufficient anymore for newer SoC-s like IPQ8074,
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IPQ6018 and more, since their networking resets require multiple bits
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to be asserted in order to properly reset the HW block completely.
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So, in order to allow asserting multiple bits add "bitmask" field to
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qcom_reset_map, and then use that bitmask value if its populated in the
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driver, if its not populated, then we just default to existing behaviour
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and calculate the bitmask on the fly.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20221107132901.489240-1-robimarko@gmail.com
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---
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drivers/clk/qcom/reset.c | 4 ++--
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drivers/clk/qcom/reset.h | 1 +
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2 files changed, 3 insertions(+), 2 deletions(-)
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--- a/drivers/clk/qcom/reset.c
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+++ b/drivers/clk/qcom/reset.c
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@@ -30,7 +30,7 @@ qcom_reset_assert(struct reset_controlle
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rst = to_qcom_reset_controller(rcdev);
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map = &rst->reset_map[id];
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- mask = BIT(map->bit);
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+ mask = map->bitmask ? map->bitmask : BIT(map->bit);
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return regmap_update_bits(rst->regmap, map->reg, mask, mask);
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}
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@@ -44,7 +44,7 @@ qcom_reset_deassert(struct reset_control
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rst = to_qcom_reset_controller(rcdev);
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map = &rst->reset_map[id];
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- mask = BIT(map->bit);
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+ mask = map->bitmask ? map->bitmask : BIT(map->bit);
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return regmap_update_bits(rst->regmap, map->reg, mask, 0);
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}
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--- a/drivers/clk/qcom/reset.h
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+++ b/drivers/clk/qcom/reset.h
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@@ -12,6 +12,7 @@ struct qcom_reset_map {
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unsigned int reg;
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u8 bit;
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u8 udelay;
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+ u32 bitmask;
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};
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struct regmap;
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