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d530ff37bf
The crypto engine in Armada 370 SoCs is currently broken. It can be
checked installing the required packages for testing openssl with hw
acceleration:
opkg install openssl-util
opkg install kmod-cryptodev
opkg install libopenssl-devcrypto
After configuring /etc/ssl/openssl.cnf to let openssl use the crypto
engine for digest operations, and performing some checksums..
md5sum 10M-file.bin
openssl md5 10M-file.bin
...we can see they don't match.
There might be an alignment or size constraint issue caused by the
idle-sram area.
Use the whole crypto sram and disable the idle-sram area to fix it. Also
disable the idle support by adding the broken-idle property to prevent
accessing the disabled idle-sram.
We don't care about disabling the idle support since it is already broken
in Armada 370 causing a huge performance loss because it disables
permanently the L2 cache. This was reported in the Openwrt forum and
elsewhere by Debian users with different board models.
Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
(cherry picked from commit 2e1ebe96c6)
30 lines
614 B
Diff
30 lines
614 B
Diff
--- a/arch/arm/boot/dts/armada-370.dtsi
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+++ b/arch/arm/boot/dts/armada-370.dtsi
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@@ -234,7 +234,7 @@
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clocks = <&gateclk 23>;
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clock-names = "cesa0";
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marvell,crypto-srams = <&crypto_sram>;
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- marvell,crypto-sram-size = <0x7e0>;
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+ marvell,crypto-sram-size = <0x800>;
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};
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};
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@@ -255,12 +255,17 @@
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* cpuidle workaround.
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*/
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idle-sram@0 {
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+ status = "disabled";
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reg = <0x0 0x20>;
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};
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};
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};
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};
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+&coherencyfab {
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+ broken-idle;
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+};
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+
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/*
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* Default UART pinctrl setting without RTS/CTS, can be overwritten on
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* board level if a different configuration is used.
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