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14940aee45
Removed upstreamed: target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch target/linux/mvebu/patches-5.4/020-arm64-dts-marvell-armada-37xx-Set-pcie_reset_pin-to-.patch The following patch does not apply to upstream any more and needs some more work to make it work fully again. I am not sure if we are still able to set the UART to a none standard baud rate. target/linux/ath79/patches-5.4/921-serial-core-add-support-for-boot-console-with-arbitr.patch These patches needed manually changes: target/linux/generic/pending-5.4/110-ehci_hcd_ignore_oc.patch target/linux/ipq806x/patches-5.4/0065-arm-override-compiler-flags.patch target/linux/layerscape/patches-5.4/804-crypto-0016-MLKU-114-1-crypto-caam-reduce-page-0-regs-access-to-.patch target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch All others updated automatically. Compile-tested on: malta/le, armvirt/64, lantiq/xrx200 Runtime-tested on: malta/le, armvirt/64, lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
55 lines
1.9 KiB
Diff
55 lines
1.9 KiB
Diff
From b2f7c18c351737c2a053c39c09ef50870fd78c06 Mon Sep 17 00:00:00 2001
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From: Vladimir Oltean <vladimir.oltean@nxp.com>
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Date: Thu, 14 Nov 2019 17:03:25 +0200
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Subject: [PATCH] net: mscc: ocelot: adjust MTU on the CPU port in NPI mode
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When using the NPI port, the DSA tag is passed through Ethernet, so the
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switch's MAC needs to accept it as it comes from the DSA master. Increase
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the MTU on the external CPU port to account for the length of the
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injection header.
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Without this patch, MTU-sized frames are dropped by the switch's CPU
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port on xmit, which is especially obvious in TCP sessions.
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Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/mscc/ocelot.c | 9 +++++++++
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drivers/net/ethernet/mscc/ocelot.h | 2 ++
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2 files changed, 11 insertions(+)
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--- a/drivers/net/ethernet/mscc/ocelot.c
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+++ b/drivers/net/ethernet/mscc/ocelot.c
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@@ -2229,9 +2229,18 @@ void ocelot_set_cpu_port(struct ocelot *
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* Only one port can be an NPI at the same time.
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*/
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if (cpu < ocelot->num_phys_ports) {
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+ int mtu = VLAN_ETH_FRAME_LEN + OCELOT_TAG_LEN;
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+
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ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M |
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QSYS_EXT_CPU_CFG_EXT_CPU_PORT(cpu),
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QSYS_EXT_CPU_CFG);
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+
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+ if (injection == OCELOT_TAG_PREFIX_SHORT)
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+ mtu += OCELOT_SHORT_PREFIX_LEN;
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+ else if (injection == OCELOT_TAG_PREFIX_LONG)
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+ mtu += OCELOT_LONG_PREFIX_LEN;
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+
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+ ocelot_port_set_mtu(ocelot, cpu, mtu);
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}
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/* CPU port Injection/Extraction configuration */
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--- a/drivers/net/ethernet/mscc/ocelot.h
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+++ b/drivers/net/ethernet/mscc/ocelot.h
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@@ -65,6 +65,8 @@ struct frame_info {
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#define IFH_REW_OP_ORIGIN_PTP 0x5
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#define OCELOT_TAG_LEN 16
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+#define OCELOT_SHORT_PREFIX_LEN 4
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+#define OCELOT_LONG_PREFIX_LEN 16
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#define OCELOT_SPEED_2500 0
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#define OCELOT_SPEED_1000 1
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