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2d5ee43dc6
Manually rebased generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch All others updated automatically. Compile-tested on: ramips/mt7621, armvirt/32 Runtime-tested on: ramips/mt7621, armvirt/32 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
61 lines
2.2 KiB
Diff
61 lines
2.2 KiB
Diff
From 6964494582f56a3882c2c53b0edbfe99eb32b2e1 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Thu, 30 Apr 2020 10:06:14 +0200
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Subject: [PATCH] PCI: aardvark: Train link immediately after enabling training
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Adding even 100ms (PCI_PM_D3COLD_WAIT) delay between enabling link
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training and starting link training causes detection issues with some
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buggy cards (such as Compex WLE900VX).
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Move the code which enables link training immediately before the one
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which starts link traning.
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This fixes detection issues of Compex WLE900VX card on Turris MOX after
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cold boot.
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Link: https://lore.kernel.org/r/20200430080625.26070-2-pali@kernel.org
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Fixes: f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready...")
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Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Acked-by: Rob Herring <robh@kernel.org>
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Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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---
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drivers/pci/controller/pci-aardvark.c | 15 +++++++++------
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1 file changed, 9 insertions(+), 6 deletions(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -311,11 +311,6 @@ static void advk_pcie_setup_hw(struct ad
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reg |= LANE_COUNT_1;
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advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
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- /* Enable link training */
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- reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
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- reg |= LINK_TRAINING_EN;
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- advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
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-
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/* Enable MSI */
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reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
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reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
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@@ -357,7 +352,15 @@ static void advk_pcie_setup_hw(struct ad
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*/
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msleep(PCI_PM_D3COLD_WAIT);
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- /* Start link training */
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+ /* Enable link training */
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+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
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+ reg |= LINK_TRAINING_EN;
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+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
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+
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+ /*
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+ * Start link training immediately after enabling it.
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+ * This solves problems for some buggy cards.
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+ */
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reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
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reg |= PCIE_CORE_LINK_TRAINING;
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advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
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