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4850bd887c
Add a new self-contained combined clock & platform driver that allows to
access the PLL hardware clocks of RTL83XX devices. Currently it provides
info about CPU, MEM and LXB clocks on RTL838X and RTL839X devices and
additionally allows to change the CPU clocks. Changing the clocks
multiple times on a DGS-1210-20 and a DGS-1210-52 already works well and
is multithreading safe on the RTL839X. Even a cpufreq initiated change
of the CPU clock works fine. Loading the driver will add some meaningful
logging.
[0.000000] rtl83xx-clk: initialized, CPU 500 MHz, MEM 300 MHz (8 Bit DDR3), LXB 200 MHz
[0.279456] rtl83xx-clk soc:clock-controller: rate setting enabled, CPU 325-600 MHz,
MEM 300-300 MHz, LXB 200-200 MHz, OVERCLOCK AT OWN RISK
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[remove trailing whitespaces, C-style SPDX comments for ASM and headers]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
151 lines
2.8 KiB
ArmAsm
151 lines
2.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Realtek RTL838X SRAM clock setters
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* Copyright (C) 2022 Markus Stockhausen <markus.stockhausen@gmx.de>
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*/
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#include <dt-bindings/clock/rtl83xx-clk.h>
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#include "clk-rtl83xx.h"
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#define rGLB $t0
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#define rCTR $t1
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#define rMSK $t2
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#define rSLP $t3
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#define rTMP $t4
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.set noreorder
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.globl rtcl_838x_dram_start
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rtcl_838x_dram_start:
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/*
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* Functions start here and should avoid access to normal memory. REMARK! Do not forget about
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* stack pointer and dirty caches that might interfere.
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*/
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.globl rtcl_838x_dram_set_rate
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.ent rtcl_838x_dram_set_rate
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rtcl_838x_dram_set_rate:
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#ifdef CONFIG_RTL838X
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li rCTR, RTL_SW_CORE_BASE
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addiu rGLB, rCTR, RTL838X_PLL_GLB_CTRL
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ori rTMP, $0, CLK_CPU
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beq $a0, rTMP, pre_cpu
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ori rTMP, $0, CLK_MEM
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beq $a0, rTMP, pre_mem
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nop
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pre_lxb:
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ori rSLP, $0, RTL838X_GLB_CTRL_LXB_PLL_READY_MASK
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addiu rCTR, rCTR, RTL838X_PLL_LXB_CTRL0
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b main_set
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ori rMSK, $0, RTL838X_GLB_CTRL_EN_LXB_PLL_MASK
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pre_mem:
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/* simple 64K data cache flush to avoid unexpected memory access */
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li rMSK, RTL_SRAM_BASE
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li rTMP, 2048
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pre_flush:
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lw $0, 0(rMSK)
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addiu rMSK, rMSK, 32
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addiu rTMP, rTMP, -1
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bne rTMP, $0, pre_flush
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lw $0, -4(rMSK)
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ori rSLP, $0, RTL838X_GLB_CTRL_MEM_PLL_READY_MASK
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addiu rCTR, rCTR, RTL838X_PLL_MEM_CTRL0
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b main_set
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ori rMSK, $0, RTL838X_GLB_CTRL_EN_MEM_PLL_MASK
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pre_cpu:
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/* switch CPU to LXB clock */
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ori rMSK, $0, RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK
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nor rMSK, rMSK, $0
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sync
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lw rTMP, 0(rGLB)
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and rTMP, rTMP, rMSK
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sw rTMP, 0(rGLB)
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sync
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ori rSLP, $0, RTL838X_GLB_CTRL_CPU_PLL_READY_MASK
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addiu rCTR, rCTR, RTL838X_PLL_CPU_CTRL0
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ori rMSK, $0, RTL838X_GLB_CTRL_EN_CPU_PLL_MASK
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main_set:
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/* disable PLL */
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nor rMSK, rMSK, 0
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sync
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lw rTMP, 0(rGLB)
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sync
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and rTMP, rTMP, rMSK
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sync
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sw rTMP, 0(rGLB)
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/* set new PLL values */
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sync
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sw $a1, 0(rCTR)
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sw $a2, 4(rCTR)
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sync
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/* enable PLL (will reset it and clear ready status) */
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nor rMSK, rMSK, 0
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sync
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lw rTMP, 0(rGLB)
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sync
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or rTMP, rTMP, rMSK
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sync
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sw rTMP, 0(rGLB)
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/* wait for PLL to become ready */
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wait_ready:
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lw rTMP, 0(rGLB)
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and rTMP, rTMP, rSLP
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bne rTMP, $0, wait_ready
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sync
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/* branch to post processing */
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ori rTMP, $0, CLK_CPU
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beq $a0, rTMP, post_cpu
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ori rTMP, $0, CLK_MEM
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beq $a0, rTMP, post_mem
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nop
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post_lxb:
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jr $ra
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nop
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post_mem:
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jr $ra
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nop
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post_cpu:
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/* stabilize clock to avoid crash, empirically determined */
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ori rSLP, $0, 0x3000
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wait_cpu:
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bnez rSLP, wait_cpu
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addiu rSLP, rSLP, -1
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/* switch CPU to PLL clock */
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ori rMSK, $0, RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK
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sync
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lw rTMP, 0(rGLB)
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or rTMP, rTMP, rMSK
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sw rTMP, 0(rGLB)
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sync
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jr $ra
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nop
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#else /* !CONFIG_RTL838X */
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jr $ra
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nop
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#endif
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.end rtcl_838x_dram_set_rate
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/*
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* End marker. Do not delete.
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*/
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.word RTL_SRAM_MARKER
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.globl rtcl_838x_dram_size
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rtcl_838x_dram_size:
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.word .-rtcl_838x_dram_start
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