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68 lines
2.5 KiB
Diff
68 lines
2.5 KiB
Diff
From 40da06da15c1718b02072687bbfb2d08f5eb9399 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Fri, 27 Aug 2021 11:27:52 +0200
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Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Rename HS-SGMMI to
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2500Base-X
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Comphy phy mode 0x3 is incorrectly named. It is not SGMII but rather
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2500Base-X mode which runs at 3.125 Gbps speed.
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Rename macro names and comments to 2500Base-X.
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Fixes: 9695375a3f4a ("phy: add A3700 COMPHY support")
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
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+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
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@@ -29,7 +29,7 @@
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#define COMPHY_FW_MODE_SATA 0x1
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#define COMPHY_FW_MODE_SGMII 0x2
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-#define COMPHY_FW_MODE_HS_SGMII 0x3
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+#define COMPHY_FW_MODE_2500BASEX 0x3
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#define COMPHY_FW_MODE_USB3H 0x4
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#define COMPHY_FW_MODE_USB3D 0x5
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#define COMPHY_FW_MODE_PCIE 0x6
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@@ -40,7 +40,7 @@
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#define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */
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#define COMPHY_FW_SPEED_2_5G 1
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-#define COMPHY_FW_SPEED_3_125G 2 /* SGMII 2.5G */
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+#define COMPHY_FW_SPEED_3_125G 2 /* 2500BASE-X */
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#define COMPHY_FW_SPEED_5G 3
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#define COMPHY_FW_SPEED_5_15625G 4 /* XFI 5G */
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#define COMPHY_FW_SPEED_6G 5
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@@ -84,14 +84,14 @@ static const struct mvebu_a3700_comphy_c
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MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,
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COMPHY_FW_MODE_SGMII),
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MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,
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- COMPHY_FW_MODE_HS_SGMII),
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+ COMPHY_FW_MODE_2500BASEX),
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/* lane 1 */
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MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0,
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COMPHY_FW_MODE_PCIE),
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MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0,
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COMPHY_FW_MODE_SGMII),
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MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0,
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- COMPHY_FW_MODE_HS_SGMII),
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+ COMPHY_FW_MODE_2500BASEX),
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/* lane 2 */
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MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0,
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COMPHY_FW_MODE_SATA),
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@@ -205,7 +205,7 @@ static int mvebu_a3700_comphy_power_on(s
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COMPHY_FW_SPEED_1_25G);
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break;
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case PHY_INTERFACE_MODE_2500BASEX:
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- dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n",
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+ dev_dbg(lane->dev, "set lane %d to 2500BASEX mode\n",
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lane->id);
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fw_param = COMPHY_FW_NET(fw_mode, lane->port,
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COMPHY_FW_SPEED_3_125G);
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