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67d998e25d
Changelog: https://cdn.kernel.org/pub/linux/kernel/v5.x/ChangeLog-5.15.145
No patches needed a rebase.
23.05 backport:
Rebased patch mediatek/100-dts-update-mt7622-rfb1.patch due to
changes introduced in commit e37aa926447f ("arm64: dts: mediatek:
mt7622: fix memory node warning check") in version v5.15.143 and we
jumped over from v5.15.139 directly to v5.15.145.
Build system: x86_64
Build-tested: ramips/tplink_archer-a6-v3
Run-tested: ramips/tplink_archer-a6-v3
23.05 backport:
Stijn:
Compile-tested: ath79/generic, ipq40xx/generic, mvebu/cortexa72, ramips/mt{7621,7620,76x8}, realtek/rtl{838x,930x}, 86/64.
Run-tested: cortexa72 (RB5009UG+S+IN), mt7621 (EAP615-Wall v1), rtl838x (GS1900-10HP, GS1900-8HP, GS108T v3).
Petr:
Compile-tested: ipq807x, mvebu/cortexa9
Run-tested: turris-omnia, prpl-haze
Tested-by: Stijn Segers <foss@volatilesystems.org> [23.05 testing]
Signed-off-by: John Audia <therealgraysky@proton.me>
Signed-off-by: Petr Štetiar <ynezz@true.cz> [23.05 refresh]
(cherry picked from commit 8de4cc77a6)
62 lines
1.7 KiB
Diff
62 lines
1.7 KiB
Diff
From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Thu, 26 Nov 2020 12:02:21 +0100
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Subject: net: phy: EEE support for rtl838x
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* rename the target to realtek
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* add refactored DSA driver
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* add latest gpio driver
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* lots of arch cleanups
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* new irq driver
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* additional boards
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Submitted-by: Bert Vermeulen <bert@biot.com>
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Submitted-by: Birger Koblitz <mail@birger-koblitz.de>
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Submitted-by: Sander Vanheule <sander@svanheule.net>
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Submitted-by: Bjørn Mork <bjorn@mork.no>
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Submitted-by: John Crispin <john@phrozen.org>
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---
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drivers/net/phy/phylink. | 14 +++++++++++--
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1 file changed, 12 insertions(+), 2 deletions(-)
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--- a/drivers/net/phy/phylink.c
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+++ b/drivers/net/phy/phylink.c
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@@ -1991,6 +1991,11 @@ int phylink_ethtool_ksettings_set(struct
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* the presence of a PHY, this should not be changed as that
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* should be determined from the media side advertisement.
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*/
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+ if (pl->phydev->drv->get_port && pl->phydev->drv->set_port) {
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+ if(pl->phydev->drv->get_port(pl->phydev) != kset->base.port) {
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+ pl->phydev->drv->set_port(pl->phydev, kset->base.port);
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+ }
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+ }
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return phy_ethtool_ksettings_set(pl->phydev, kset);
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}
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@@ -2294,8 +2299,11 @@ int phylink_ethtool_get_eee(struct phyli
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ASSERT_RTNL();
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- if (pl->phydev)
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+ if (pl->phydev) {
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+ if (pl->phydev->drv->get_eee)
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+ return pl->phydev->drv->get_eee(pl->phydev, eee);
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ret = phy_ethtool_get_eee(pl->phydev, eee);
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+ }
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return ret;
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}
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@@ -2312,8 +2320,11 @@ int phylink_ethtool_set_eee(struct phyli
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ASSERT_RTNL();
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- if (pl->phydev)
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+ if (pl->phydev) {
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+ if (pl->phydev->drv->set_eee)
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+ return pl->phydev->drv->set_eee(pl->phydev, eee);
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ret = phy_ethtool_set_eee(pl->phydev, eee);
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+ }
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return ret;
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}
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