mirror of
https://github.com/openwrt/openwrt.git
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8e294af41b
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.58 All patches automatically rebased. Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/glinet_gl-mt6000, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Run-tested: x86/64/AMD Cezanne, flogic/glinet_gl-mt6000, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/16758 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
420 lines
13 KiB
Diff
420 lines
13 KiB
Diff
From 928ce2dd884412ac8afbecadc87bfd8efe511a11 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Fri, 10 Sep 2021 17:20:45 +0100
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Subject: [PATCH 0518/1085] net: macb: Also set DMA coherent mask
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macb: Add device tree properties that allow configuration of the AXI max pipeline register
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net: macb: add support for ethtool interrupt moderation configuration
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Only global throttling of rx or tx by time quanta is supported.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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macb: add platform device shutdown function. Prevents AXI master over PCIE from hanging when the host is rebooted.
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net: macb: increase polling interval for MDIO completion
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MDIO is a slow bus (single-digit MHz). Polling at 1us intervals
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is a bit aggressive, so increase to 100us as the transaction
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usually takes 100-200us to complete.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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net: macb: Several patches for RP1
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64-bit RX fix
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Also set DMA coherent mask
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Add device tree properties that allow configuration of the AXI max
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pipeline register
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Add support for ethtool interrupt moderation configuration
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Only global throttling of rx or tx by time quanta is supported.
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Add platform device shutdown function. Prevents AXI master over PCIE
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from hanging when the host is rebooted.
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Increase polling interval for MDIO completion
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MDIO is a slow bus (single-digit MHz). Polling at 1us intervals
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is a bit aggressive, so increase to 100us as the transaction
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usually takes 100-200us to complete.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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net: macb: Support the phy-reset-gpios property
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Allow a PHY to be reset with an optional GPIO. The reset duration can
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be specified in milliseconds - the default is 10ms.
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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drivers: net: macb: close device on driver shutdown
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Fix some suspicious locking and instead call into macb_close, which
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deregisters and frees all resources the corresponding macb_open
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claimed.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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net: macb: add hack to prevent TX stalls in a quiet system
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See https://github.com/raspberrypi/linux-2712/issues/89
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There is some critical window during TX where a further write to the
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TSTART bit while TX is active does not cause newly queued TX descriptors
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to be consumed.
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For now "wait a bit, then try anyway" seems to work.
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Requires further investigation, but this unsticks NFS reliably.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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net: macb: set default interrupt moderation for GEM hardware
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Defaulting to intmod = 0 is antisocial, as the MAC can generate over
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130,000 interrupts per second. 50us is a sensible default.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/net/ethernet/cadence/macb.h | 25 ++++
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drivers/net/ethernet/cadence/macb_main.c | 152 ++++++++++++++++++++++-
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2 files changed, 175 insertions(+), 2 deletions(-)
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--- a/drivers/net/ethernet/cadence/macb.h
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+++ b/drivers/net/ethernet/cadence/macb.h
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@@ -85,6 +85,8 @@
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#define GEM_PBUFRXCUT 0x0044 /* RX Partial Store and Forward */
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#define GEM_JML 0x0048 /* Jumbo Max Length */
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#define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */
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+#define GEM_AMP 0x0054 /* AXI Max Pipeline */
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+#define GEM_INTMOD 0x005c /* Interrupt moderation */
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#define GEM_HRB 0x0080 /* Hash Bottom */
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#define GEM_HRT 0x0084 /* Hash Top */
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#define GEM_SA1B 0x0088 /* Specific1 Bottom */
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@@ -347,6 +349,21 @@
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#define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
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#define GEM_ADDR64_SIZE 1
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+/* Bitfields in AMP */
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+#define GEM_AR2R_MAX_PIPE_OFFSET 0 /* Maximum number of outstanding AXI read requests */
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+#define GEM_AR2R_MAX_PIPE_SIZE 8
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+#define GEM_AW2W_MAX_PIPE_OFFSET 8 /* Maximum number of outstanding AXI write requests */
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+#define GEM_AW2W_MAX_PIPE_SIZE 8
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+#define GEM_AW2B_FILL_OFFSET 16 /* Select wether the max AW2W transactions operates between: */
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+#define GEM_AW2B_FILL_AW2W 0 /* 0: the AW to W AXI channel */
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+#define GEM_AW2B_FILL_AW2B 1 /* 1: AW to B channel */
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+#define GEM_AW2B_FILL_SIZE 1
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+
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+/* Bitfields in INTMOD */
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+#define GEM_RX_MODERATION_OFFSET 0 /* RX interrupt moderation */
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+#define GEM_RX_MODERATION_SIZE 8
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+#define GEM_TX_MODERATION_OFFSET 16 /* TX interrupt moderation */
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+#define GEM_TX_MODERATION_SIZE 8
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/* Bitfields in PBUFRXCUT */
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#define GEM_ENCUTTHRU_OFFSET 31 /* Enable RX partial store and forward */
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@@ -807,6 +824,7 @@
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})
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#define MACB_READ_NSR(bp) macb_readl(bp, NSR)
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+#define MACB_READ_TSR(bp) macb_readl(bp, TSR)
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/* struct macb_dma_desc - Hardware DMA descriptor
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* @addr: DMA address of data buffer
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@@ -1222,6 +1240,7 @@ struct macb_queue {
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dma_addr_t tx_ring_dma;
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struct work_struct tx_error_task;
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bool txubr_pending;
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+ bool tx_pending;
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struct napi_struct napi_tx;
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dma_addr_t rx_ring_dma;
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@@ -1285,9 +1304,15 @@ struct macb {
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u32 caps;
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unsigned int dma_burst_length;
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+ u8 aw2w_max_pipe;
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+ u8 ar2r_max_pipe;
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+ bool use_aw2b_fill;
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phy_interface_t phy_interface;
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+ struct gpio_desc *phy_reset_gpio;
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+ int phy_reset_ms;
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+
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/* AT91RM9200 transmit queue (1 on wire + 1 queued) */
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struct macb_tx_skb rm9200_txq[2];
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unsigned int max_tx_length;
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--- a/drivers/net/ethernet/cadence/macb_main.c
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+++ b/drivers/net/ethernet/cadence/macb_main.c
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@@ -40,6 +40,9 @@
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#include <linux/firmware/xlnx-zynqmp.h>
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#include "macb.h"
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+static unsigned int txdelay = 35;
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+module_param(txdelay, uint, 0644);
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+
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/* This structure is only used for MACB on SiFive FU540 devices */
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struct sifive_fu540_macb_mgmt {
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void __iomem *reg;
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@@ -334,7 +337,7 @@ static int macb_mdio_wait_for_idle(struc
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u32 val;
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return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
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- 1, MACB_MDIO_TIMEOUT);
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+ 100, MACB_MDIO_TIMEOUT);
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}
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static int macb_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
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@@ -493,6 +496,19 @@ mdio_pm_exit:
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return status;
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}
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+static int macb_mdio_reset(struct mii_bus *bus)
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+{
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+ struct macb *bp = bus->priv;
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+
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+ if (bp->phy_reset_gpio) {
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+ gpiod_set_value_cansleep(bp->phy_reset_gpio, 1);
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+ msleep(bp->phy_reset_ms);
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+ gpiod_set_value_cansleep(bp->phy_reset_gpio, 0);
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+ }
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+
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+ return 0;
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+}
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+
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static void macb_init_buffers(struct macb *bp)
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{
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struct macb_queue *queue;
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@@ -977,6 +993,7 @@ static int macb_mii_init(struct macb *bp
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bp->mii_bus->write = &macb_mdio_write_c22;
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bp->mii_bus->read_c45 = &macb_mdio_read_c45;
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bp->mii_bus->write_c45 = &macb_mdio_write_c45;
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+ bp->mii_bus->reset = &macb_mdio_reset;
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snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
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bp->pdev->name, bp->pdev->id);
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bp->mii_bus->priv = bp;
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@@ -1648,6 +1665,11 @@ static int macb_rx(struct macb_queue *qu
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macb_init_rx_ring(queue);
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queue_writel(queue, RBQP, queue->rx_ring_dma);
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+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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+ if (bp->hw_dma_cap & HW_DMA_CAP_64B)
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+ macb_writel(bp, RBQPH,
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+ upper_32_bits(queue->rx_ring_dma));
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+#endif
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macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
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@@ -1948,8 +1970,9 @@ static irqreturn_t macb_interrupt(int ir
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queue_writel(queue, ISR, MACB_BIT(TCOMP) |
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MACB_BIT(TXUBR));
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- if (status & MACB_BIT(TXUBR)) {
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+ if (status & MACB_BIT(TXUBR) || queue->tx_pending) {
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queue->txubr_pending = true;
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+ queue->tx_pending = 0;
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wmb(); // ensure softirq can see update
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}
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@@ -2402,6 +2425,11 @@ static netdev_tx_t macb_start_xmit(struc
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skb_tx_timestamp(skb);
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spin_lock_irq(&bp->lock);
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+
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+ /* TSTART write might get dropped, so make the IRQ retrigger a buffer read */
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+ if (macb_readl(bp, TSR) & MACB_BIT(TGO))
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+ queue->tx_pending = 1;
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+
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macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
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spin_unlock_irq(&bp->lock);
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@@ -2776,6 +2804,37 @@ static void macb_configure_dma(struct ma
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}
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}
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+static void gem_init_axi(struct macb *bp)
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+{
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+ u32 amp;
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+
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+ /* AXI pipeline setup - don't touch values unless specified in device
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+ * tree. Some hardware could have reset values > 1.
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+ */
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+ amp = gem_readl(bp, AMP);
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+
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+ if (bp->use_aw2b_fill)
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+ amp = GEM_BFINS(AW2B_FILL, bp->use_aw2b_fill, amp);
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+ if (bp->aw2w_max_pipe)
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+ amp = GEM_BFINS(AW2W_MAX_PIPE, bp->aw2w_max_pipe, amp);
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+ if (bp->ar2r_max_pipe)
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+ amp = GEM_BFINS(AR2R_MAX_PIPE, bp->ar2r_max_pipe, amp);
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+
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+ gem_writel(bp, AMP, amp);
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+}
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+
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+static void gem_init_intmod(struct macb *bp)
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+{
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+ unsigned int throttle;
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+ u32 intmod = 0;
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+
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+ /* Use sensible interrupt moderation thresholds (50us rx and tx) */
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+ throttle = (1000 * 50) / 800;
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+ intmod = GEM_BFINS(TX_MODERATION, throttle, intmod);
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+ intmod = GEM_BFINS(RX_MODERATION, throttle, intmod);
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+ gem_writel(bp, INTMOD, intmod);
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+}
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+
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static void macb_init_hw(struct macb *bp)
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{
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u32 config;
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@@ -2804,6 +2863,11 @@ static void macb_init_hw(struct macb *bp
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if (bp->caps & MACB_CAPS_JUMBO)
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bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
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+ if (macb_is_gem(bp)) {
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+ gem_init_axi(bp);
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+ gem_init_intmod(bp);
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+ }
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+
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macb_configure_dma(bp);
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/* Enable RX partial store and forward and set watermark */
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@@ -3165,6 +3229,52 @@ static void gem_get_ethtool_strings(stru
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}
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}
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+static int gem_set_coalesce(struct net_device *dev,
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+ struct ethtool_coalesce *ec,
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+ struct kernel_ethtool_coalesce *kernel_coal,
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+ struct netlink_ext_ack *extack)
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+{
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+ struct macb *bp = netdev_priv(dev);
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+ unsigned int tx_throttle;
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+ unsigned int rx_throttle;
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+ u32 intmod = 0;
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+
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+ /* GEM has simple IRQ throttling support. RX and TX interrupts
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+ * are separately moderated on 800ns quantums, with no support
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+ * for frame coalescing.
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+ */
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+
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+ /* Max is 255 * 0.8us = 204us. Zero implies no moderation. */
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+ if (ec->rx_coalesce_usecs > 204 || ec->tx_coalesce_usecs > 204)
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+ return -EINVAL;
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+
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+ tx_throttle = (1000 * ec->tx_coalesce_usecs) / 800;
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+ rx_throttle = (1000 * ec->rx_coalesce_usecs) / 800;
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+
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+ intmod = GEM_BFINS(TX_MODERATION, tx_throttle, intmod);
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+ intmod = GEM_BFINS(RX_MODERATION, rx_throttle, intmod);
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+
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+ gem_writel(bp, INTMOD, intmod);
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+
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+ return 0;
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+}
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+
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+static int gem_get_coalesce(struct net_device *dev,
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+ struct ethtool_coalesce *ec,
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+ struct kernel_ethtool_coalesce *kernel_coal,
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+ struct netlink_ext_ack *extack)
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+{
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+ struct macb *bp = netdev_priv(dev);
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+ u32 intmod;
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+
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+ intmod = gem_readl(bp, INTMOD);
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+
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+ ec->tx_coalesce_usecs = (GEM_BFEXT(TX_MODERATION, intmod) * 800) / 1000;
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+ ec->rx_coalesce_usecs = (GEM_BFEXT(RX_MODERATION, intmod) * 800) / 1000;
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+
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+ return 0;
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+}
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+
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static struct net_device_stats *macb_get_stats(struct net_device *dev)
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{
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struct macb *bp = netdev_priv(dev);
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@@ -3757,6 +3867,8 @@ static const struct ethtool_ops macb_eth
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};
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static const struct ethtool_ops gem_ethtool_ops = {
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+ .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
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+ ETHTOOL_COALESCE_TX_USECS,
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.get_regs_len = macb_get_regs_len,
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.get_regs = macb_get_regs,
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.get_wol = macb_get_wol,
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@@ -3766,6 +3878,8 @@ static const struct ethtool_ops gem_etht
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.get_ethtool_stats = gem_get_ethtool_stats,
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.get_strings = gem_get_ethtool_strings,
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.get_sset_count = gem_get_sset_count,
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+ .get_coalesce = gem_get_coalesce,
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+ .set_coalesce = gem_set_coalesce,
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.get_link_ksettings = macb_get_link_ksettings,
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.set_link_ksettings = macb_set_link_ksettings,
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.get_ringparam = macb_get_ringparam,
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@@ -5062,6 +5176,11 @@ static int macb_probe(struct platform_de
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}
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}
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}
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+
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+ device_property_read_u8(&pdev->dev, "cdns,aw2w-max-pipe", &bp->aw2w_max_pipe);
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+ device_property_read_u8(&pdev->dev, "cdns,ar2r-max-pipe", &bp->ar2r_max_pipe);
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+ bp->use_aw2b_fill = device_property_read_bool(&pdev->dev, "cdns,use-aw2b-fill");
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+
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spin_lock_init(&bp->lock);
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/* setup capabilities */
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@@ -5117,6 +5236,21 @@ static int macb_probe(struct platform_de
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else
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bp->phy_interface = interface;
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+ /* optional PHY reset-related properties */
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+ bp->phy_reset_gpio = devm_gpiod_get_optional(&pdev->dev, "phy-reset",
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+ GPIOD_OUT_LOW);
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+ if (IS_ERR(bp->phy_reset_gpio)) {
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+ dev_err(&pdev->dev, "Failed to obtain phy-reset gpio\n");
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+ err = PTR_ERR(bp->phy_reset_gpio);
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+ goto err_out_free_netdev;
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+ }
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+
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+ bp->phy_reset_ms = 10;
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+ of_property_read_u32(np, "phy-reset-duration", &bp->phy_reset_ms);
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+ /* A sane reset duration should not be longer than 1s */
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+ if (bp->phy_reset_ms > 1000)
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+ bp->phy_reset_ms = 1000;
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+
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/* IP specific init */
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err = init(pdev);
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if (err)
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@@ -5193,6 +5327,19 @@ static int macb_remove(struct platform_d
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return 0;
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}
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+static void macb_shutdown(struct platform_device *pdev)
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+{
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+ struct net_device *dev;
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+
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+ dev = platform_get_drvdata(pdev);
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+
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+ rtnl_lock();
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+ netif_device_detach(dev);
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+ if (netif_running(dev))
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+ dev_close(dev);
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+ rtnl_unlock();
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+}
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+
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static int __maybe_unused macb_suspend(struct device *dev)
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{
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struct net_device *netdev = dev_get_drvdata(dev);
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@@ -5407,6 +5554,7 @@ static const struct dev_pm_ops macb_pm_o
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static struct platform_driver macb_driver = {
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.probe = macb_probe,
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.remove = macb_remove,
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+ .shutdown = macb_shutdown,
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.driver = {
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.name = "macb",
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.of_match_table = of_match_ptr(macb_dt_ids),
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