ExternalVendorCode/openwrt
1
0
Fork 0
mirror of https://github.com/openwrt/openwrt.git synced 2025-03-15 08:40:58 +00:00
Code Issues Actions3 Packages Projects Releases Wiki Activity
6c8cc86295
openwrt/package/boot/uboot-mediatek/patches/060-07-net-mediatek-add-support-for-10GBASE-R.patch
Shiji Yang 24ade65ab5 uboot-mediatek: backport mtk_eth fixes from u-boot next 
This patch series will provide better support for Mediatek
ethernet and add support for Airoha AN8855.

Signed-off-by: Shiji Yang <yangshiji66@qq.com>
2025-02-09 21:50:58 +00:00

148 lines
6.1 KiB
Diff
Raw Blame History

From ad0c47109e4c9f6297aa247d8bbf7131438bc435 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:50 +0800
Subject: [PATCH 07/10] net: mediatek: add support for 10GBASE-R
This patch adds support for 10GBASE-R interface mode
Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 83 +++++++++++++++++++++++++++++++++++++++++--
1 file changed, 81 insertions(+), 2 deletions(-)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1246,6 +1246,7 @@ static int mtk_phy_start(struct mtk_eth_
if (!priv->force_mode) {
if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
mtk_xphy_link_adjust(priv);
else
@@ -1425,6 +1426,71 @@ static void mtk_usxgmii_setup_phya_an_10
udelay(400);
}
+static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv)
+{
+ regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C);
+ regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
+ regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000);
+ ndelay(1020);
+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000);
+ ndelay(1020);
+
+ regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
+ regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
+ regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
+ regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
+ regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
+ regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
+ regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
+ regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
+ regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
+ regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
+ regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
+ regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
+ regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
+ regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
+ regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
+ regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
+ regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
+ regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
+ regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
+ regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
+ regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
+ regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
+ ndelay(1020);
+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
+ regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
+ regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
+ regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
+ regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
+ regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
+ regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
+ regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100);
+ regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000);
+ regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000);
+ regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
+ if (priv->gmac_id == 2)
+ regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400);
+ regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
+ regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
+ udelay(150);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
+ ndelay(1020);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
+ udelay(15);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
+ ndelay(1020);
+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
+ udelay(100);
+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
+ regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
+ udelay(400);
+}
+
static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
{
mtk_xfi_pll_enable(priv);
@@ -1432,6 +1498,13 @@ static void mtk_usxgmii_an_init(struct m
mtk_usxgmii_setup_phya_an_10000(priv);
}
+static void mtk_10gbaser_init(struct mtk_eth_priv *priv)
+{
+ mtk_xfi_pll_enable(priv);
+ mtk_usxgmii_reset(priv);
+ mtk_usxgmii_setup_phya_force_10000(priv);
+}
+
static void mtk_mac_init(struct mtk_eth_priv *priv)
{
int i, sgmii_sel_mask = 0, ge_mode = 0;
@@ -1532,6 +1605,9 @@ static void mtk_xmac_init(struct mtk_eth
case PHY_INTERFACE_MODE_USXGMII:
mtk_usxgmii_an_init(priv);
break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ mtk_10gbaser_init(priv);
+ break;
default:
break;
}
@@ -1541,7 +1617,8 @@ static void mtk_xmac_init(struct mtk_eth
SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
0);
- if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII &&
+ if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) &&
priv->gmac_id == 1) {
mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
@@ -1843,6 +1920,7 @@ static int mtk_eth_probe(struct udevice
/* Set MAC mode */
if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
mtk_xmac_init(priv);
else
@@ -1977,7 +2055,8 @@ static int mtk_eth_of_to_plat(struct ude
/* Upstream linux use mediatek,pnswap instead of pn_swap */
priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") ||
ofnode_read_bool(args.node, "mediatek,pnswap");
- } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
+ } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
+ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) {
/* get corresponding usxgmii phandle */
ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
NULL, 0, 0, &args);
Reference in New Issue View Git Blame Copy Permalink