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158 lines
5.4 KiB
Diff
158 lines
5.4 KiB
Diff
From 034dd6241b55ab2256eecb845e941fa9b45da38e Mon Sep 17 00:00:00 2001
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From: Yunhui Cui <yunhui.cui@nxp.com>
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Date: Thu, 28 Apr 2016 17:03:57 +0800
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Subject: [PATCH 110/113] mtd: spi-nor: fsl-quad: add flash S25FS extra
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support
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[context adjustment]
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not apply changes of arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
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There are some boards have the same QSPI controller but have
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different vendor flash, So, the controller can use the same
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compatible and share the driver, just for a different flash to do
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the appropriate adaptation. Based on this, we need add the vendor
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field in spi-nor, Because we will use the field to distribute
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corresponding LUT for different flash operations.
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Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
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Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
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Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
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---
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drivers/mtd/spi-nor/fsl-quadspi.c | 47 ++++++++++++++++++++++++++++++-------
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drivers/mtd/spi-nor/spi-nor.c | 5 ++--
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include/linux/mtd/spi-nor.h | 1 +
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3 files changed, 42 insertions(+), 11 deletions(-)
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--- a/drivers/mtd/spi-nor/fsl-quadspi.c
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+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
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@@ -213,6 +213,9 @@
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#define QUADSPI_MIN_IOMAP SZ_4M
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+#define FLASH_VENDOR_SPANSION_FS "s25fs"
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+#define SPANSION_S25FS_FAMILY (1 << 1)
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+
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enum fsl_qspi_devtype {
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FSL_QUADSPI_VYBRID,
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FSL_QUADSPI_IMX6SX,
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@@ -329,6 +332,18 @@ static inline int has_added_amba_base_in
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return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL;
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}
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+static u32 fsl_get_nor_vendor(struct spi_nor *nor)
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+{
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+ u32 vendor_id;
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+
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+ if (nor->vendor) {
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+ if (memcmp(nor->vendor, FLASH_VENDOR_SPANSION_FS,
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+ sizeof(FLASH_VENDOR_SPANSION_FS) - 1))
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+ vendor_id = SPANSION_S25FS_FAMILY;
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+ }
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+ return vendor_id;
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+}
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+
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/*
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* R/W functions for big- or little-endian registers:
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* The qSPI controller's endian is independent of the CPU core's endian.
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@@ -394,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl
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int rxfifo = q->devtype_data->rxfifo;
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u32 lut_base;
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int i;
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- const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
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+ u32 vendor;
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struct spi_nor *nor = &q->nor[0];
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u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
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u8 read_op = nor->read_opcode;
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u8 read_dm = nor->read_dummy;
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+ vendor = fsl_get_nor_vendor(nor);
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+
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fsl_qspi_unlock_lut(q);
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/* Clear all the LUT table */
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@@ -418,12 +435,25 @@ static void fsl_qspi_init_lut(struct fsl
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LUT1(FSL_READ, PAD1, rxfifo),
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base + QUADSPI_LUT(lut_base + 1));
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} else if (nor->flash_read == SPI_NOR_QUAD) {
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- qspi_writel(q, LUT0(CMD, PAD1, read_op) |
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- LUT1(ADDR, PAD1, addrlen),
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- base + QUADSPI_LUT(lut_base));
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- qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
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- LUT1(FSL_READ, PAD4, rxfifo),
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- base + QUADSPI_LUT(lut_base + 1));
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+ if (q->nor_size == 0x4000000) {
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+ read_op = 0xEC;
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+ qspi_writel(q,
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+ LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD4, addrlen),
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+ base + QUADSPI_LUT(lut_base));
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+ qspi_writel(q,
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+ LUT0(MODE, PAD4, 0xff) | LUT1(DUMMY, PAD4, read_dm),
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+ base + QUADSPI_LUT(lut_base + 1));
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+ qspi_writel(q,
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+ LUT0(FSL_READ, PAD4, rxfifo),
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+ base + QUADSPI_LUT(lut_base + 2));
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+ } else {
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+ qspi_writel(q, LUT0(CMD, PAD1, read_op) |
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+ LUT1(ADDR, PAD1, addrlen),
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+ base + QUADSPI_LUT(lut_base));
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+ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
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+ LUT1(FSL_READ, PAD4, rxfifo),
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+ base + QUADSPI_LUT(lut_base + 1));
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+ }
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} else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
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/* read mode : 1-4-4, such as Spansion s25fl128s. */
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qspi_writel(q, LUT0(CMD, PAD1, read_op)
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@@ -510,7 +540,8 @@ static void fsl_qspi_init_lut(struct fsl
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* use the same value 0x65. But it indicates different meaning.
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*/
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lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
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- if (devtype_data->devtype == FSL_QUADSPI_LS2080A) {
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+
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+ if (vendor == SPANSION_S25FS_FAMILY) {
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/*
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* Read any device register.
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* Used for Spansion S25FS-S family flash only.
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -798,7 +798,6 @@ static const struct flash_info spi_nor_i
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{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)},
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- { "s25fs512s", INFO6(0x010220, 0x4d0081, 128 * 1024, 512, 0)},
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{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
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{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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@@ -965,11 +964,9 @@ static int spansion_s25fs_disable_4kb_er
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ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
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if (ret)
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return ret;
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-/*
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if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
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return -EPERM;
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-*/
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return 0;
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}
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@@ -1343,6 +1340,8 @@ int spi_nor_scan(struct spi_nor *nor, co
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if (!mtd->name)
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mtd->name = dev_name(dev);
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+ if (info->name)
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+ nor->vendor = info->name;
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mtd->priv = nor;
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mtd->type = MTD_NORFLASH;
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mtd->writesize = 1;
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--- a/include/linux/mtd/spi-nor.h
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+++ b/include/linux/mtd/spi-nor.h
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@@ -172,6 +172,7 @@ struct spi_nor {
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bool sst_write_second;
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u32 flags;
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u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
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+ char *vendor;
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int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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