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9d4145efe5
The BCM4331 supports a PCIe max request size of 512 bytes and uses that, but the PCIe controller in the BCM4706 just supports 128 Bytes and that causes a DMA error for packages bigger than 126 bytes. This fixes the problem by setting the BCM4331 also to 128 Bytes. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 37709
168 lines
5.2 KiB
Diff
168 lines
5.2 KiB
Diff
bcma patch adding bcma_core_pci_up() and bcma_core_pci_down(), this gets
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called by b43 and brcmsmac
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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--- a/drivers/bcma/driver_pci.c
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+++ b/drivers/bcma/driver_pci.c
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@@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
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}
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-static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
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+static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
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{
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u32 v;
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int i;
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@@ -55,7 +55,7 @@ static void bcma_pcie_mdio_set_phy(struc
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}
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}
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-static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
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+static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
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{
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int max_retries = 10;
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u16 ret = 0;
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@@ -98,7 +98,7 @@ static u16 bcma_pcie_mdio_read(struct bc
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return ret;
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}
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-static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
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+static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
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u8 address, u16 data)
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{
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int max_retries = 10;
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@@ -137,6 +137,13 @@ static void bcma_pcie_mdio_write(struct
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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}
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+static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
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+ u8 address, u16 data)
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+{
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+ bcma_pcie_mdio_write(pc, device, address, data);
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+ return bcma_pcie_mdio_read(pc, device, address);
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+}
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+
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/**************************************************
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* Workarounds.
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**************************************************/
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@@ -203,6 +210,25 @@ static void bcma_core_pci_config_fixup(s
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}
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}
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+static void bcma_core_pci_power_save(struct bcma_drv_pci *pc, bool up)
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+{
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+ u16 data;
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+
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+ if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
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+ data = up ? 0x74 : 0x7C;
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+ bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
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+ BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
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+ bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
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+ BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
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+ } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
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+ data = up ? 0x75 : 0x7D;
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+ bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
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+ BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
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+ bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
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+ BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
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+ }
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+}
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+
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/**************************************************
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* Init.
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**************************************************/
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@@ -262,7 +288,7 @@ out:
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}
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EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
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-void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
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+static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
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{
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u32 w;
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@@ -274,4 +300,38 @@ void bcma_core_pci_extend_L1timer(struct
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bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
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bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
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}
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-EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
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+
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+void bcma_core_pci_up(struct bcma_bus *bus)
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+{
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+ struct bcma_drv_pci *pc;
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+
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+ if (bus->hosttype != BCMA_HOSTTYPE_PCI)
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+ return;
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+
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+ pc = &bus->drv_pci[0];
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+
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+ bcma_core_pci_power_save(pc, true);
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+
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+ bcma_core_pci_extend_L1timer(pc, true);
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+
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+ if ((pc->core->id.rev == 18 || pc->core->id.rev == 19) &&
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+ bus->boardinfo.vendor != PCI_VENDOR_ID_APPLE) {
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+ pcie_set_readrq(bus->host_pci, 128);
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+ }
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+}
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+EXPORT_SYMBOL_GPL(bcma_core_pci_up);
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+
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+void bcma_core_pci_down(struct bcma_bus *bus)
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+{
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+ struct bcma_drv_pci *pc;
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+
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+ if (bus->hosttype != BCMA_HOSTTYPE_PCI)
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+ return;
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+
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+ pc = &bus->drv_pci[0];
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+
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+ bcma_core_pci_extend_L1timer(pc, false);
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+
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+ bcma_core_pci_power_save(pc, false);
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+}
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+EXPORT_SYMBOL_GPL(bcma_core_pci_down);
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--- a/include/linux/bcma/bcma_driver_pci.h
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+++ b/include/linux/bcma/bcma_driver_pci.h
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@@ -181,10 +181,31 @@ struct pci_dev;
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#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
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+#define BCMA_CORE_PCI_
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+
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+/* MDIO devices (SERDES modules) */
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+#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
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+#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
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+#define BCMA_CORE_PCI_MDIO_BLK0 0x800
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+#define BCMA_CORE_PCI_MDIO_BLK1 0x801
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+#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
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+#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
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+#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
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+#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
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+#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
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+#define BCMA_CORE_PCI_MDIO_BLK2 0x802
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+#define BCMA_CORE_PCI_MDIO_BLK3 0x803
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+#define BCMA_CORE_PCI_MDIO_BLK4 0x804
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+#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
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+#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
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+#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
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+#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
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+
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/* PCIE Root Capability Register bits (Host mode only) */
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#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
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struct bcma_drv_pci;
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+struct bcma_bus;
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#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
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struct bcma_drv_pci_host {
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@@ -219,7 +240,8 @@ struct bcma_drv_pci {
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extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
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extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
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struct bcma_device *core, bool enable);
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-extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
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+extern void bcma_core_pci_up(struct bcma_bus *bus);
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+extern void bcma_core_pci_down(struct bcma_bus *bus);
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extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
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extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
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