mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 06:08:08 +00:00
3711557bdf
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.36
Manually rebased:
generic/hack-6.6/765-mxl-gpy-control-LED-reg-from-DT.patch
bcm27xx/patches-6.6/950-0536-dmaengine-dw-axi-dmac-Fixes-for-RP1.patch
Removed upstreamed:
bmips/patches-6.6/010-v6.10-mips-bmips-BCM6358-make-sure-CBR-is-correctly-set.patch[1]
All other patches automatically rebased.
1. 7c9644a7b5
Build system: x86/64
Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Signed-off-by: John Audia <therealgraysky@proton.me>
64 lines
2.1 KiB
Diff
64 lines
2.1 KiB
Diff
From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001
|
|
From: Daniel Golle <daniel@makrotopia.org>
|
|
Date: Thu, 6 Apr 2023 23:36:50 +0100
|
|
Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink
|
|
|
|
MAC drivers using phylink expect SGMII in-band-status to be switched off
|
|
when attached to a PHY. Make sure this is the case also for mxl-gpy which
|
|
keeps SGMII in-band-status in case of SGMII interface mode is used.
|
|
|
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
|
---
|
|
drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++---
|
|
1 file changed, 16 insertions(+), 3 deletions(-)
|
|
|
|
--- a/drivers/net/phy/mxl-gpy.c
|
|
+++ b/drivers/net/phy/mxl-gpy.c
|
|
@@ -385,8 +385,11 @@ static bool gpy_2500basex_chk(struct phy
|
|
|
|
phydev->speed = SPEED_2500;
|
|
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
|
|
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
|
- VSPEC1_SGMII_CTRL_ANEN, 0);
|
|
+
|
|
+ if (!phydev->phylink)
|
|
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
|
+ VSPEC1_SGMII_CTRL_ANEN, 0);
|
|
+
|
|
return true;
|
|
}
|
|
|
|
@@ -437,6 +440,14 @@ static int gpy_config_aneg(struct phy_de
|
|
u32 adv;
|
|
int ret;
|
|
|
|
+ /* Disable SGMII auto-negotiation if using phylink */
|
|
+ if (phydev->phylink) {
|
|
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
|
+ VSPEC1_SGMII_CTRL_ANEN, 0);
|
|
+ if (ret < 0)
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
if (phydev->autoneg == AUTONEG_DISABLE) {
|
|
/* Configure half duplex with genphy_setup_forced,
|
|
* because genphy_c45_pma_setup_forced does not support.
|
|
@@ -559,6 +570,8 @@ static int gpy_update_interface(struct p
|
|
switch (phydev->speed) {
|
|
case SPEED_2500:
|
|
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
|
|
+ if (phydev->phylink)
|
|
+ break;
|
|
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
|
VSPEC1_SGMII_CTRL_ANEN, 0);
|
|
if (ret < 0) {
|
|
@@ -572,7 +585,7 @@ static int gpy_update_interface(struct p
|
|
case SPEED_100:
|
|
case SPEED_10:
|
|
phydev->interface = PHY_INTERFACE_MODE_SGMII;
|
|
- if (gpy_sgmii_aneg_en(phydev))
|
|
+ if (phydev->phylink || gpy_sgmii_aneg_en(phydev))
|
|
break;
|
|
/* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
|
|
* if ANEG is disabled (in 2500-BaseX mode).
|