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31116661ff
update to the version of the driver that is on its way upstream Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 47898
101 lines
3.0 KiB
Diff
101 lines
3.0 KiB
Diff
From 5ad283c69029a519681ed453e7f7ddf250c10559 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 18 Nov 2015 03:51:24 +0100
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Subject: [PATCH 507/513] net-next: mediatek: add support for rt3883
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Add support for rt3883 and its smaller version rt3662. They both have a single
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gBit port that will normally be attached to an external phy of switch.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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Signed-off-by: Michael Lee <igvtee@gmail.com>
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---
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drivers/net/ethernet/mediatek/soc_rt3883.c | 75 ++++++++++++++++++++++++++++
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1 file changed, 75 insertions(+)
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create mode 100644 drivers/net/ethernet/mediatek/soc_rt3883.c
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diff --git a/drivers/net/ethernet/mediatek/soc_rt3883.c b/drivers/net/ethernet/mediatek/soc_rt3883.c
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new file mode 100644
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index 0000000..7f34d4d
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/soc_rt3883.c
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@@ -0,0 +1,75 @@
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+/* This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
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+ * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
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+ * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
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+ */
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+
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+#include <linux/module.h>
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+
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+#include <asm/mach-ralink/ralink_regs.h>
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+
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+#include "mtk_eth_soc.h"
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+#include "mdio_rt2880.h"
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+
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+#define RT3883_RSTCTRL_FE BIT(21)
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+
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+static void rt3883_fe_reset(void)
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+{
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+ fe_reset(RT3883_RSTCTRL_FE);
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+}
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+
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+static int rt3883_fwd_config(struct fe_priv *priv)
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+{
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+ int ret;
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+
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+ ret = fe_set_clock_cycle(priv);
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+ if (ret)
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+ return ret;
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+
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+ fe_fwd_config(priv);
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+ fe_w32(FE_PSE_FQFC_CFG_256Q, FE_PSE_FQ_CFG);
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+ fe_csum_config(priv);
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+
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+ return ret;
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+}
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+
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+static void rt3883_init_data(struct fe_soc_data *data,
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+ struct net_device *netdev)
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+{
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+ struct fe_priv *priv = netdev_priv(netdev);
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+
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+ priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
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+ FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
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+ netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
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+ NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
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+}
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+
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+static struct fe_soc_data rt3883_data = {
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+ .init_data = rt3883_init_data,
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+ .reset_fe = rt3883_fe_reset,
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+ .fwd_config = rt3883_fwd_config,
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+ .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
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+ .rx_int = FE_RX_DONE_INT,
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+ .tx_int = FE_TX_DONE_INT,
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+ .status_int = FE_CNT_GDM_AF,
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+ .checksum_bit = RX_DMA_L4VALID,
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+ .mdio_read = rt2880_mdio_read,
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+ .mdio_write = rt2880_mdio_write,
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+ .mdio_adjust_link = rt2880_mdio_link_adjust,
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+ .port_init = rt2880_port_init,
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+};
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+
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+const struct of_device_id of_fe_match[] = {
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+ { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
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+ {},
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+};
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+
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+MODULE_DEVICE_TABLE(of, of_fe_match);
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--
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1.7.10.4
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