mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 06:57:57 +00:00
86171d4d6e
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.27
Removed upstreamed:
pending-6.6/981-gcc-plugins-stackleak-Avoid-.head.txt.section.patch[1]
All patches automatically rebased.
1. 9dff96b8b3
Build system: x86/64
Build-tested: flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3, x86/64/AMD Cezanne
Run-tested: flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3, x86/64/AMD Cezanne
Signed-off-by: John Audia <therealgraysky@proton.me>
176 lines
6.8 KiB
Diff
176 lines
6.8 KiB
Diff
From 6ab3d50b106c9aea123a80551a6c9deace83b914 Mon Sep 17 00:00:00 2001
|
|
From: Qiang Yu <quic_qianyu@quicinc.com>
|
|
Date: Tue, 7 Nov 2023 16:14:49 +0800
|
|
Subject: [PATCH] bus: mhi: host: Add a separate timeout parameter for waiting
|
|
ready
|
|
|
|
Some devices(eg. SDX75) take longer than expected (default, 8 seconds) to
|
|
set ready after reboot. Hence add optional ready timeout parameter and pass
|
|
the appropriate timeout value to mhi_poll_reg_field() to wait enough for
|
|
device ready as part of power up sequence.
|
|
|
|
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
|
|
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
|
Link: https://lore.kernel.org/r/1699344890-87076-2-git-send-email-quic_qianyu@quicinc.com
|
|
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
|
---
|
|
drivers/bus/mhi/host/init.c | 1 +
|
|
drivers/bus/mhi/host/internal.h | 2 +-
|
|
drivers/bus/mhi/host/main.c | 5 +++--
|
|
drivers/bus/mhi/host/pm.c | 24 +++++++++++++++++-------
|
|
include/linux/mhi.h | 4 ++++
|
|
5 files changed, 26 insertions(+), 10 deletions(-)
|
|
|
|
--- a/drivers/bus/mhi/host/init.c
|
|
+++ b/drivers/bus/mhi/host/init.c
|
|
@@ -882,6 +882,7 @@ static int parse_config(struct mhi_contr
|
|
if (!mhi_cntrl->timeout_ms)
|
|
mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS;
|
|
|
|
+ mhi_cntrl->ready_timeout_ms = config->ready_timeout_ms;
|
|
mhi_cntrl->bounce_buf = config->use_bounce_buf;
|
|
mhi_cntrl->buffer_len = config->buf_len;
|
|
if (!mhi_cntrl->buffer_len)
|
|
--- a/drivers/bus/mhi/host/internal.h
|
|
+++ b/drivers/bus/mhi/host/internal.h
|
|
@@ -324,7 +324,7 @@ int __must_check mhi_read_reg_field(stru
|
|
u32 *out);
|
|
int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl,
|
|
void __iomem *base, u32 offset, u32 mask,
|
|
- u32 val, u32 delayus);
|
|
+ u32 val, u32 delayus, u32 timeout_ms);
|
|
void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base,
|
|
u32 offset, u32 val);
|
|
int __must_check mhi_write_reg_field(struct mhi_controller *mhi_cntrl,
|
|
--- a/drivers/bus/mhi/host/main.c
|
|
+++ b/drivers/bus/mhi/host/main.c
|
|
@@ -40,10 +40,11 @@ int __must_check mhi_read_reg_field(stru
|
|
|
|
int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl,
|
|
void __iomem *base, u32 offset,
|
|
- u32 mask, u32 val, u32 delayus)
|
|
+ u32 mask, u32 val, u32 delayus,
|
|
+ u32 timeout_ms)
|
|
{
|
|
int ret;
|
|
- u32 out, retry = (mhi_cntrl->timeout_ms * 1000) / delayus;
|
|
+ u32 out, retry = (timeout_ms * 1000) / delayus;
|
|
|
|
while (retry--) {
|
|
ret = mhi_read_reg_field(mhi_cntrl, base, offset, mask, &out);
|
|
--- a/drivers/bus/mhi/host/pm.c
|
|
+++ b/drivers/bus/mhi/host/pm.c
|
|
@@ -171,6 +171,7 @@ int mhi_ready_state_transition(struct mh
|
|
enum mhi_pm_state cur_state;
|
|
struct device *dev = &mhi_cntrl->mhi_dev->dev;
|
|
u32 interval_us = 25000; /* poll register field every 25 milliseconds */
|
|
+ u32 timeout_ms;
|
|
int ret, i;
|
|
|
|
/* Check if device entered error state */
|
|
@@ -181,14 +182,18 @@ int mhi_ready_state_transition(struct mh
|
|
|
|
/* Wait for RESET to be cleared and READY bit to be set by the device */
|
|
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
|
|
- MHICTRL_RESET_MASK, 0, interval_us);
|
|
+ MHICTRL_RESET_MASK, 0, interval_us,
|
|
+ mhi_cntrl->timeout_ms);
|
|
if (ret) {
|
|
dev_err(dev, "Device failed to clear MHI Reset\n");
|
|
return ret;
|
|
}
|
|
|
|
+ timeout_ms = mhi_cntrl->ready_timeout_ms ?
|
|
+ mhi_cntrl->ready_timeout_ms : mhi_cntrl->timeout_ms;
|
|
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHISTATUS,
|
|
- MHISTATUS_READY_MASK, 1, interval_us);
|
|
+ MHISTATUS_READY_MASK, 1, interval_us,
|
|
+ timeout_ms);
|
|
if (ret) {
|
|
dev_err(dev, "Device failed to enter MHI Ready\n");
|
|
return ret;
|
|
@@ -487,7 +492,7 @@ static void mhi_pm_disable_transition(st
|
|
|
|
/* Wait for the reset bit to be cleared by the device */
|
|
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
|
|
- MHICTRL_RESET_MASK, 0, 25000);
|
|
+ MHICTRL_RESET_MASK, 0, 25000, mhi_cntrl->timeout_ms);
|
|
if (ret)
|
|
dev_err(dev, "Device failed to clear MHI Reset\n");
|
|
|
|
@@ -500,8 +505,8 @@ static void mhi_pm_disable_transition(st
|
|
if (!MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
|
|
/* wait for ready to be set */
|
|
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs,
|
|
- MHISTATUS,
|
|
- MHISTATUS_READY_MASK, 1, 25000);
|
|
+ MHISTATUS, MHISTATUS_READY_MASK,
|
|
+ 1, 25000, mhi_cntrl->timeout_ms);
|
|
if (ret)
|
|
dev_err(dev, "Device failed to enter READY state\n");
|
|
}
|
|
@@ -1125,7 +1130,8 @@ int mhi_async_power_up(struct mhi_contro
|
|
if (state == MHI_STATE_SYS_ERR) {
|
|
mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
|
|
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
|
|
- MHICTRL_RESET_MASK, 0, interval_us);
|
|
+ MHICTRL_RESET_MASK, 0, interval_us,
|
|
+ mhi_cntrl->timeout_ms);
|
|
if (ret) {
|
|
dev_info(dev, "Failed to reset MHI due to syserr state\n");
|
|
goto error_exit;
|
|
@@ -1216,14 +1222,18 @@ EXPORT_SYMBOL_GPL(mhi_power_down);
|
|
int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
|
|
{
|
|
int ret = mhi_async_power_up(mhi_cntrl);
|
|
+ u32 timeout_ms;
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
+ /* Some devices need more time to set ready during power up */
|
|
+ timeout_ms = mhi_cntrl->ready_timeout_ms ?
|
|
+ mhi_cntrl->ready_timeout_ms : mhi_cntrl->timeout_ms;
|
|
wait_event_timeout(mhi_cntrl->state_event,
|
|
MHI_IN_MISSION_MODE(mhi_cntrl->ee) ||
|
|
MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
|
|
- msecs_to_jiffies(mhi_cntrl->timeout_ms));
|
|
+ msecs_to_jiffies(timeout_ms));
|
|
|
|
ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT;
|
|
if (ret)
|
|
--- a/include/linux/mhi.h
|
|
+++ b/include/linux/mhi.h
|
|
@@ -266,6 +266,7 @@ struct mhi_event_config {
|
|
* struct mhi_controller_config - Root MHI controller configuration
|
|
* @max_channels: Maximum number of channels supported
|
|
* @timeout_ms: Timeout value for operations. 0 means use default
|
|
+ * @ready_timeout_ms: Timeout value for waiting device to be ready (optional)
|
|
* @buf_len: Size of automatically allocated buffers. 0 means use default
|
|
* @num_channels: Number of channels defined in @ch_cfg
|
|
* @ch_cfg: Array of defined channels
|
|
@@ -277,6 +278,7 @@ struct mhi_event_config {
|
|
struct mhi_controller_config {
|
|
u32 max_channels;
|
|
u32 timeout_ms;
|
|
+ u32 ready_timeout_ms;
|
|
u32 buf_len;
|
|
u32 num_channels;
|
|
const struct mhi_channel_config *ch_cfg;
|
|
@@ -330,6 +332,7 @@ struct mhi_controller_config {
|
|
* @pm_mutex: Mutex for suspend/resume operation
|
|
* @pm_lock: Lock for protecting MHI power management state
|
|
* @timeout_ms: Timeout in ms for state transitions
|
|
+ * @ready_timeout_ms: Timeout in ms for waiting device to be ready (optional)
|
|
* @pm_state: MHI power management state
|
|
* @db_access: DB access states
|
|
* @ee: MHI device execution environment
|
|
@@ -419,6 +422,7 @@ struct mhi_controller {
|
|
struct mutex pm_mutex;
|
|
rwlock_t pm_lock;
|
|
u32 timeout_ms;
|
|
+ u32 ready_timeout_ms;
|
|
u32 pm_state;
|
|
u32 db_access;
|
|
enum mhi_ee_type ee;
|