openwrt/target/linux/ramips/dts/WR1200JS.dts
Chuanhong Guo be2b61e4f1 ramips: drop m25p,chunked-io from dts
This option was a spi nor hack which is dropped in commit
bcf4a5f474 ("ramips: remove chunked-io patch and set spi->max_transfer_size instead")

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com> [edit message]
2019-02-05 19:37:30 +01:00

147 lines
2.3 KiB
Plaintext

/dts-v1/;
#include "mt7621.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "youhua,wr1200js", "mediatek,mt7621-soc";
model = "YouHua WR1200JS";
aliases {
led-boot = &led_wps;
led-failsafe = &led_wps;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200";
};
leds {
compatible = "gpio-leds";
internet {
label = "wr1200js:blue:internet";
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
led_wps: wps {
label = "wr1200js:blue:wps";
gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
};
usb {
label = "wr1200js:blue:usb";
gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
linux,default-trigger = "usbport";
};
};
keys {
compatible = "gpio-keys-polled";
poll-interval = <20>;
reset {
label = "reset";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
wifi {
label = "wifi";
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
};
};
&spi0 {
status = "okay";
m25p80@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "u-boot-env";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
partition@50000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x50000 0xfb0000>;
};
};
};
};
&pcie {
status = "okay";
};
&pcie0 {
mt76@0,0 {
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x0000>;
};
};
&pcie1 {
mt76@0,0 {
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x8000>;
ieee80211-freq-limit = <5000000 6000000>;
led {
led-sources = <2>;
led-active-low;
};
};
};
&ethernet {
mtd-mac-address = <&factory 0xe000>;
};
&pinctrl {
state_default: pinctrl0 {
gpio {
ralink,group = "i2c", "uart2", "uart3", "wdt";
ralink,function = "gpio";
};
};
};