mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-26 17:01:14 +00:00
20402106a3
As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
185 lines
5.0 KiB
Diff
185 lines
5.0 KiB
Diff
From f634bd6444b004d080a6bbcee812f95669d6a91f Mon Sep 17 00:00:00 2001
|
|
From: Martin Sperl <kernel@martin.sperl.org>
|
|
Date: Mon, 29 Feb 2016 15:43:57 +0000
|
|
Subject: [PATCH 263/423] clk: bcm2835: add missing osc and per clocks
|
|
|
|
Add AVE0, DFT, GP0, GP1, GP2, SLIM, SMI, TEC, DPI, CAM0, CAM1, DSI0E,
|
|
and DSI1E. PULSE is not added because it has an extra divider.
|
|
|
|
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
|
|
Signed-off-by: Eric Anholt <eric@anholt.net>
|
|
Reviewed-by: Eric Anholt <eric@anholt.net>
|
|
(cherry picked from commit d3d6f15fd376e3dbba851724057b112558c70b79)
|
|
---
|
|
drivers/clk/bcm/clk-bcm2835.c | 90 +++++++++++++++++++++++++++++++++++++
|
|
include/dt-bindings/clock/bcm2835.h | 14 ++++++
|
|
2 files changed, 104 insertions(+)
|
|
|
|
--- a/drivers/clk/bcm/clk-bcm2835.c
|
|
+++ b/drivers/clk/bcm/clk-bcm2835.c
|
|
@@ -117,6 +117,8 @@
|
|
#define CM_SDCCTL 0x1a8
|
|
#define CM_SDCDIV 0x1ac
|
|
#define CM_ARMCTL 0x1b0
|
|
+#define CM_AVEOCTL 0x1b8
|
|
+#define CM_AVEODIV 0x1bc
|
|
#define CM_EMMCCTL 0x1c0
|
|
#define CM_EMMCDIV 0x1c4
|
|
|
|
@@ -1610,6 +1612,12 @@ static const struct bcm2835_clk_desc clk
|
|
.div_reg = CM_TSENSDIV,
|
|
.int_bits = 5,
|
|
.frac_bits = 0),
|
|
+ [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
|
|
+ .name = "tec",
|
|
+ .ctl_reg = CM_TECCTL,
|
|
+ .div_reg = CM_TECDIV,
|
|
+ .int_bits = 6,
|
|
+ .frac_bits = 0),
|
|
|
|
/* clocks with vpu parent mux */
|
|
[BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
|
|
@@ -1624,6 +1632,7 @@ static const struct bcm2835_clk_desc clk
|
|
.div_reg = CM_ISPDIV,
|
|
.int_bits = 4,
|
|
.frac_bits = 8),
|
|
+
|
|
/*
|
|
* Secondary SDRAM clock. Used for low-voltage modes when the PLL
|
|
* in the SDRAM controller can't be used.
|
|
@@ -1655,6 +1664,36 @@ static const struct bcm2835_clk_desc clk
|
|
.is_vpu_clock = true),
|
|
|
|
/* clocks with per parent mux */
|
|
+ [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
|
|
+ .name = "aveo",
|
|
+ .ctl_reg = CM_AVEOCTL,
|
|
+ .div_reg = CM_AVEODIV,
|
|
+ .int_bits = 4,
|
|
+ .frac_bits = 0),
|
|
+ [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
|
|
+ .name = "cam0",
|
|
+ .ctl_reg = CM_CAM0CTL,
|
|
+ .div_reg = CM_CAM0DIV,
|
|
+ .int_bits = 4,
|
|
+ .frac_bits = 8),
|
|
+ [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
|
|
+ .name = "cam1",
|
|
+ .ctl_reg = CM_CAM1CTL,
|
|
+ .div_reg = CM_CAM1DIV,
|
|
+ .int_bits = 4,
|
|
+ .frac_bits = 8),
|
|
+ [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
|
|
+ .name = "dft",
|
|
+ .ctl_reg = CM_DFTCTL,
|
|
+ .div_reg = CM_DFTDIV,
|
|
+ .int_bits = 5,
|
|
+ .frac_bits = 0),
|
|
+ [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
|
|
+ .name = "dpi",
|
|
+ .ctl_reg = CM_DPICTL,
|
|
+ .div_reg = CM_DPIDIV,
|
|
+ .int_bits = 4,
|
|
+ .frac_bits = 8),
|
|
|
|
/* Arasan EMMC clock */
|
|
[BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
|
|
@@ -1663,6 +1702,29 @@ static const struct bcm2835_clk_desc clk
|
|
.div_reg = CM_EMMCDIV,
|
|
.int_bits = 4,
|
|
.frac_bits = 8),
|
|
+
|
|
+ /* General purpose (GPIO) clocks */
|
|
+ [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
|
|
+ .name = "gp0",
|
|
+ .ctl_reg = CM_GP0CTL,
|
|
+ .div_reg = CM_GP0DIV,
|
|
+ .int_bits = 12,
|
|
+ .frac_bits = 12,
|
|
+ .is_mash_clock = true),
|
|
+ [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
|
|
+ .name = "gp1",
|
|
+ .ctl_reg = CM_GP1CTL,
|
|
+ .div_reg = CM_GP1DIV,
|
|
+ .int_bits = 12,
|
|
+ .frac_bits = 12,
|
|
+ .is_mash_clock = true),
|
|
+ [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
|
|
+ .name = "gp2",
|
|
+ .ctl_reg = CM_GP2CTL,
|
|
+ .div_reg = CM_GP2DIV,
|
|
+ .int_bits = 12,
|
|
+ .frac_bits = 12),
|
|
+
|
|
/* HDMI state machine */
|
|
[BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
|
|
.name = "hsm",
|
|
@@ -1684,12 +1746,26 @@ static const struct bcm2835_clk_desc clk
|
|
.int_bits = 12,
|
|
.frac_bits = 12,
|
|
.is_mash_clock = true),
|
|
+ [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
|
|
+ .name = "slim",
|
|
+ .ctl_reg = CM_SLIMCTL,
|
|
+ .div_reg = CM_SLIMDIV,
|
|
+ .int_bits = 12,
|
|
+ .frac_bits = 12,
|
|
+ .is_mash_clock = true),
|
|
+ [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
|
|
+ .name = "smi",
|
|
+ .ctl_reg = CM_SMICTL,
|
|
+ .div_reg = CM_SMIDIV,
|
|
+ .int_bits = 4,
|
|
+ .frac_bits = 8),
|
|
[BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
|
|
.name = "uart",
|
|
.ctl_reg = CM_UARTCTL,
|
|
.div_reg = CM_UARTDIV,
|
|
.int_bits = 10,
|
|
.frac_bits = 12),
|
|
+
|
|
/* TV encoder clock. Only operating frequency is 108Mhz. */
|
|
[BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
|
|
.name = "vec",
|
|
@@ -1698,6 +1774,20 @@ static const struct bcm2835_clk_desc clk
|
|
.int_bits = 4,
|
|
.frac_bits = 0),
|
|
|
|
+ /* dsi clocks */
|
|
+ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
|
|
+ .name = "dsi0e",
|
|
+ .ctl_reg = CM_DSI0ECTL,
|
|
+ .div_reg = CM_DSI0EDIV,
|
|
+ .int_bits = 4,
|
|
+ .frac_bits = 8),
|
|
+ [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
|
|
+ .name = "dsi1e",
|
|
+ .ctl_reg = CM_DSI1ECTL,
|
|
+ .div_reg = CM_DSI1EDIV,
|
|
+ .int_bits = 4,
|
|
+ .frac_bits = 8),
|
|
+
|
|
/* the gates */
|
|
|
|
/*
|
|
--- a/include/dt-bindings/clock/bcm2835.h
|
|
+++ b/include/dt-bindings/clock/bcm2835.h
|
|
@@ -50,3 +50,17 @@
|
|
#define BCM2835_PLLA_CCP2 33
|
|
#define BCM2835_PLLD_DSI0 34
|
|
#define BCM2835_PLLD_DSI1 35
|
|
+
|
|
+#define BCM2835_CLOCK_AVEO 36
|
|
+#define BCM2835_CLOCK_DFT 37
|
|
+#define BCM2835_CLOCK_GP0 38
|
|
+#define BCM2835_CLOCK_GP1 39
|
|
+#define BCM2835_CLOCK_GP2 40
|
|
+#define BCM2835_CLOCK_SLIM 41
|
|
+#define BCM2835_CLOCK_SMI 42
|
|
+#define BCM2835_CLOCK_TEC 43
|
|
+#define BCM2835_CLOCK_DPI 44
|
|
+#define BCM2835_CLOCK_CAM0 45
|
|
+#define BCM2835_CLOCK_CAM1 46
|
|
+#define BCM2835_CLOCK_DSI0E 47
|
|
+#define BCM2835_CLOCK_DSI1E 48
|