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0806f8fc80
Following changes are made to the Lantiq kernel patches: 0001-MIPS-lantiq-add-pcie-driver.patch The pci header isn't included by the of_pci header any longer 0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch Due to the merge of grx390 and ar10 clocks, extend support to grx390 0025-NET-MIPS-lantiq-adds-xrx200-legacy.patch The do_carrier arguments was dropped from phy_link_change. The phylib has always sets the third parameter to true so the flag is always changed anyway. of_get_phy_mode() returns an error, or 0 on success, and pass a pointer, of type phy_interface_t, where the phy mode should be stored now. So far an error wasn't considered. Print at least an error message if something unexpected happens. The stuck queue is now passed to xrx200_tx_timeout (the timeout handler) but not used so far. 0028-NET-lantiq-various-etop-fixes.patch ioremap has provided non-cached semantics by default since the Linux 2.6 days and was removed with kernel version 5.6. of_get_phy_mode() returns an error, or 0 on success, and pass a pointer, of type phy_interface_t, where the phy mode should be stored now. So far an error wasn't considered. Print at least an error message if something unexpected happens. 0042-arch-mips-increase-io_space_limit.patch Move IO space extension to laniq specific file Signed-off-by: Mathias Kresin <dev@kresin.me>
181 lines
4.5 KiB
Diff
181 lines
4.5 KiB
Diff
--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -2425,6 +2425,12 @@ config MIPS_VPE_LOADER
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Includes a loader for loading an elf relocatable object
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onto another VPE and running it.
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+config IFX_VPE_EXT
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+ bool "IFX APRP Extensions"
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+ depends on MIPS_VPE_LOADER
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+ help
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+ IFX included extensions in APRP
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+
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config MIPS_VPE_LOADER_CMP
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bool
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default "y"
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--- a/arch/mips/include/asm/vpe.h
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+++ b/arch/mips/include/asm/vpe.h
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@@ -127,4 +127,13 @@ void cleanup_tc(struct tc *tc);
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int __init vpe_module_init(void);
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void __exit vpe_module_exit(void);
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+
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+/* For the explanation of the APIs please refer the section "MT APRP Kernel
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+ * Programming" in AR9 SW Architecture Specification
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+ */
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+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags);
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+int32_t vpe1_sw_stop(uint32_t flags);
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+uint32_t vpe1_get_load_addr(uint32_t flags);
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+uint32_t vpe1_get_max_mem(uint32_t flags);
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+
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#endif /* _ASM_VPE_H */
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--- a/arch/mips/kernel/vpe-mt.c
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+++ b/arch/mips/kernel/vpe-mt.c
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@@ -29,6 +29,7 @@ int vpe_run(struct vpe *v)
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struct vpe_notifications *notifier;
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unsigned int vpeflags;
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struct tc *t;
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+ unsigned long physical_memsize = 0L;
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/* check we are the Master VPE */
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local_irq_save(flags);
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@@ -417,6 +418,8 @@ int __init vpe_module_init(void)
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}
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v->ntcs = hw_tcs - aprp_cpu_index();
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+ write_tc_c0_tcbind((read_tc_c0_tcbind() &
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+ ~TCBIND_CURVPE) | 1);
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/* add the tc to the list of this vpe's tc's. */
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list_add(&t->tc, &v->tc);
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@@ -519,3 +522,47 @@ void __exit vpe_module_exit(void)
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release_vpe(v);
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}
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}
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+
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+#ifdef CONFIG_IFX_VPE_EXT
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+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags)
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+{
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+ enum vpe_state state;
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+ struct vpe *v = get_vpe(tclimit);
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+ struct vpe_notifications *not;
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+
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+ if (tcmask || flags) {
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+ pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n");
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+ return -1;
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+ }
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+
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+ state = xchg(&v->state, VPE_STATE_INUSE);
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+ if (state != VPE_STATE_UNUSED) {
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+ vpe_stop(v);
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+
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+ list_for_each_entry(not, &v->notify, list) {
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+ not->stop(tclimit);
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+ }
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+ }
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+
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+ v->__start = (unsigned long)sw_start_addr;
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+
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+ if (!vpe_run(v)) {
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+ pr_debug("VPE loader: VPE1 running successfully\n");
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+ return 0;
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+ }
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+ return -1;
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+}
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+EXPORT_SYMBOL(vpe1_sw_start);
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+
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+int32_t vpe1_sw_stop(uint32_t flags)
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+{
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+ struct vpe *v = get_vpe(tclimit);
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+
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+ if (!vpe_free(v)) {
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+ pr_debug("RP Stopped\n");
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+ return 0;
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+ } else
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+ return -1;
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+}
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+EXPORT_SYMBOL(vpe1_sw_stop);
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+#endif
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--- a/arch/mips/kernel/vpe.c
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+++ b/arch/mips/kernel/vpe.c
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@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = {
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.tc_list = LIST_HEAD_INIT(vpecontrol.tc_list)
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};
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+#ifdef CONFIG_IFX_VPE_EXT
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+unsigned int vpe1_load_addr;
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+
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+static int __init load_address(char *str)
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+{
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+ get_option(&str, &vpe1_load_addr);
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+ return 1;
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+}
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+__setup("vpe1_load_addr=", load_address);
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+
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+static unsigned int vpe1_mem;
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+static int __init vpe1mem(char *str)
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+{
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+ vpe1_mem = memparse(str, &str);
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+ return 1;
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+}
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+__setup("vpe1_mem=", vpe1mem);
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+
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+uint32_t vpe1_get_load_addr(uint32_t flags)
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+{
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+ return vpe1_load_addr;
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+}
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+EXPORT_SYMBOL(vpe1_get_load_addr);
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+
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+uint32_t vpe1_get_max_mem(uint32_t flags)
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+{
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+ if (!vpe1_mem)
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+ return P_SIZE;
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+ else
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+ return vpe1_mem;
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+}
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+EXPORT_SYMBOL(vpe1_get_max_mem);
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+
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+#endif
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+
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/* get the vpe associated with this minor */
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struct vpe *get_vpe(int minor)
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{
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--- a/arch/mips/lantiq/prom.c
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+++ b/arch/mips/lantiq/prom.c
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@@ -34,10 +34,14 @@ unsigned long physical_memsize = 0L;
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*/
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static struct ltq_soc_info soc_info;
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+/* for Multithreading (APRP), vpe.c will use it */
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+unsigned long cp0_memsize;
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+
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const char *get_system_type(void)
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{
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return soc_info.sys_type;
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}
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+EXPORT_SYMBOL(ltq_soc_type);
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int ltq_soc_type(void)
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{
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--- a/arch/mips/include/asm/mipsmtregs.h
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+++ b/arch/mips/include/asm/mipsmtregs.h
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@@ -32,6 +32,9 @@
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#define read_c0_vpeconf1() __read_32bit_c0_register($1, 3)
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#define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val)
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+#define read_c0_vpeopt() __read_32bit_c0_register($1, 7)
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+#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val)
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+
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#define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
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#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
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@@ -378,6 +381,8 @@ do { \
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#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
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#define read_vpe_c0_vpeconf1() mftc0(1, 3)
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#define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val)
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+#define read_vpe_c0_vpeopt() mftc0(1, 7)
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+#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val)
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#define read_vpe_c0_count() mftc0(9, 0)
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#define write_vpe_c0_count(val) mttc0(9, 0, val)
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#define read_vpe_c0_status() mftc0(12, 0)
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