mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 15:02:32 +00:00
20ea6adbf1
Build system: x86_64 Build-tested: bcm2708, bcm2709, bcm2710, bcm2711 Run-tested: bcm2708/RPiB+, bcm2709/RPi3B, bcm2710/RPi3B, bcm2711/RPi4B Signed-off-by: Marty Jones <mj8263788@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
41 lines
1.4 KiB
Diff
41 lines
1.4 KiB
Diff
From 70887a91ef710cada7d43ac2ec93280bb53d540f Mon Sep 17 00:00:00 2001
|
|
From: Maxime Ripard <maxime@cerno.tech>
|
|
Date: Wed, 13 Apr 2022 16:22:49 +0200
|
|
Subject: [PATCH] drm/vc4: kms: Use maximum FIFO load for the HVS clock
|
|
rate
|
|
|
|
The core clock computation takes into account both the load due to the
|
|
input (ie, planes) and its output (ie, encoders).
|
|
|
|
However, while the input load needs to consider all the planes, and thus
|
|
sum all of their associated loads, the output happens mostly in
|
|
parallel.
|
|
|
|
Therefore, we need to consider only the maximum of all the output loads,
|
|
and not the sum like we were doing. This resulted in a clock rate way
|
|
too high which could be discarded for being too high by the clock
|
|
framework.
|
|
|
|
Since recent changes, the clock framework will even downright reject it,
|
|
leading to a core clock being too low for its current needs.
|
|
|
|
Fixes: 16e101051f32 ("drm/vc4: Increase the core clock based on HVS load")
|
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
|
---
|
|
drivers/gpu/drm/vc4/vc4_kms.c | 4 +++-
|
|
1 file changed, 3 insertions(+), 1 deletion(-)
|
|
|
|
--- a/drivers/gpu/drm/vc4/vc4_kms.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
|
|
@@ -939,7 +939,9 @@ vc4_core_clock_atomic_check(struct drm_a
|
|
continue;
|
|
|
|
num_outputs++;
|
|
- cob_rate += hvs_new_state->fifo_state[i].fifo_load;
|
|
+ cob_rate = max_t(unsigned long,
|
|
+ hvs_new_state->fifo_state[i].fifo_load,
|
|
+ cob_rate);
|
|
}
|
|
|
|
pixel_rate = load_state->hvs_load;
|