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047695a029
This reverts commit 51397d7d95.
There are some unresolved random crashes on WRT1900AC v1 that still need
to be sorted out
Signed-off-by: Felix Fietkau <nbd@nbd.name>
279 lines
8.3 KiB
Diff
279 lines
8.3 KiB
Diff
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Date: Wed, 9 Dec 2015 18:23:49 +0100
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Subject: [PATCH] net: mvneta: Associate RX queues with each CPU
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We enable the percpu interrupt for all the CPU and we just associate a
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CPU to a few queue at the neta level. The mapping between the CPUs and
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the queues is static. The queues are associated to the CPU module the
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number of CPUs. However currently we only use on RX queue for a given
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Ethernet port.
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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--- a/drivers/net/ethernet/marvell/mvneta.c
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+++ b/drivers/net/ethernet/marvell/mvneta.c
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@@ -110,9 +110,16 @@
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#define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
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#define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
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#define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
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+#define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
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#define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
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-/* Exception Interrupt Port/Queue Cause register */
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+/* Exception Interrupt Port/Queue Cause register
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+ *
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+ * Their behavior depend of the mapping done using the PCPX2Q
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+ * registers. For a given CPU if the bit associated to a queue is not
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+ * set, then for the register a read from this CPU will always return
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+ * 0 and a write won't do anything
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+ */
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#define MVNETA_INTR_NEW_CAUSE 0x25a0
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#define MVNETA_INTR_NEW_MASK 0x25a4
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@@ -820,7 +827,13 @@ static void mvneta_port_up(struct mvneta
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mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
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/* Enable all initialized RXQs. */
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- mvreg_write(pp, MVNETA_RXQ_CMD, BIT(pp->rxq_def));
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+ for (queue = 0; queue < rxq_number; queue++) {
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+ struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
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+
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+ if (rxq->descs != NULL)
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+ q_map |= (1 << queue);
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+ }
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+ mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
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}
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/* Stop the Ethernet port activity */
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@@ -1026,6 +1039,7 @@ static void mvneta_defaults_set(struct m
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int cpu;
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int queue;
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u32 val;
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+ int max_cpu = num_present_cpus();
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/* Clear all Cause registers */
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mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
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@@ -1041,13 +1055,23 @@ static void mvneta_defaults_set(struct m
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/* Enable MBUS Retry bit16 */
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mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
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- /* Set CPU queue access map - all CPUs have access to all RX
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- * queues and to all TX queues
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+ /* Set CPU queue access map. CPUs are assigned to the RX
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+ * queues modulo their number and all the TX queues are
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+ * assigned to the CPU associated to the default RX queue.
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*/
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- for_each_present_cpu(cpu)
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- mvreg_write(pp, MVNETA_CPU_MAP(cpu),
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- (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
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- MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
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+ for_each_present_cpu(cpu) {
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+ int rxq_map = 0, txq_map = 0;
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+ int rxq;
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+
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+ for (rxq = 0; rxq < rxq_number; rxq++)
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+ if ((rxq % max_cpu) == cpu)
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+ rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
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+
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+ if (cpu == rxq_def)
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+ txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
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+
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+ mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
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+ }
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/* Reset RX and TX DMAs */
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mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
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@@ -2174,6 +2198,7 @@ static int mvneta_poll(struct napi_struc
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{
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int rx_done = 0;
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u32 cause_rx_tx;
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+ int rx_queue;
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struct mvneta_port *pp = netdev_priv(napi->dev);
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struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
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@@ -2205,8 +2230,15 @@ static int mvneta_poll(struct napi_struc
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/* For the case where the last mvneta_poll did not process all
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* RX packets
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*/
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+ rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
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+
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cause_rx_tx |= port->cause_rx_tx;
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- rx_done = mvneta_rx(pp, budget, &pp->rxqs[pp->rxq_def]);
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+
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+ if (rx_queue) {
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+ rx_queue = rx_queue - 1;
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+ rx_done = mvneta_rx(pp, budget, &pp->rxqs[rx_queue]);
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+ }
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+
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budget -= rx_done;
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if (budget > 0) {
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@@ -2419,19 +2451,27 @@ static void mvneta_cleanup_txqs(struct m
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/* Cleanup all Rx queues */
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static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
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{
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- mvneta_rxq_deinit(pp, &pp->rxqs[pp->rxq_def]);
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+ int queue;
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+
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+ for (queue = 0; queue < txq_number; queue++)
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+ mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
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}
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/* Init all Rx queues */
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static int mvneta_setup_rxqs(struct mvneta_port *pp)
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{
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- int err = mvneta_rxq_init(pp, &pp->rxqs[pp->rxq_def]);
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- if (err) {
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- netdev_err(pp->dev, "%s: can't create rxq=%d\n",
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- __func__, pp->rxq_def);
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- mvneta_cleanup_rxqs(pp);
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- return err;
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+ int queue;
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+
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+ for (queue = 0; queue < rxq_number; queue++) {
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+ int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
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+
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+ if (err) {
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+ netdev_err(pp->dev, "%s: can't create rxq=%d\n",
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+ __func__, queue);
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+ mvneta_cleanup_rxqs(pp);
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+ return err;
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+ }
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}
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return 0;
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@@ -2455,6 +2495,19 @@ static int mvneta_setup_txqs(struct mvne
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return 0;
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}
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+static void mvneta_percpu_unmask_interrupt(void *arg)
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+{
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+ struct mvneta_port *pp = arg;
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+
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+ /* All the queue are unmasked, but actually only the ones
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+ * maped to this CPU will be unmasked
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+ */
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+ mvreg_write(pp, MVNETA_INTR_NEW_MASK,
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+ MVNETA_RX_INTR_MASK_ALL |
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+ MVNETA_TX_INTR_MASK_ALL |
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+ MVNETA_MISCINTR_INTR_MASK);
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+}
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+
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static void mvneta_start_dev(struct mvneta_port *pp)
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{
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unsigned int cpu;
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@@ -2472,11 +2525,10 @@ static void mvneta_start_dev(struct mvne
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napi_enable(&port->napi);
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}
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- /* Unmask interrupts */
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- mvreg_write(pp, MVNETA_INTR_NEW_MASK,
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- MVNETA_RX_INTR_MASK(rxq_number) |
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- MVNETA_TX_INTR_MASK(txq_number) |
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- MVNETA_MISCINTR_INTR_MASK);
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+ /* Unmask interrupts. It has to be done from each CPU */
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+ for_each_online_cpu(cpu)
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+ smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
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+ pp, true);
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mvreg_write(pp, MVNETA_INTR_MISC_MASK,
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MVNETA_CAUSE_PHY_STATUS_CHANGE |
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MVNETA_CAUSE_LINK_CHANGE |
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@@ -2752,22 +2804,35 @@ static void mvneta_percpu_disable(void *
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static void mvneta_percpu_elect(struct mvneta_port *pp)
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{
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- int online_cpu_idx, cpu, i = 0;
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+ int online_cpu_idx, max_cpu, cpu, i = 0;
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online_cpu_idx = pp->rxq_def % num_online_cpus();
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+ max_cpu = num_present_cpus();
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for_each_online_cpu(cpu) {
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- if (i == online_cpu_idx)
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- /* Enable per-CPU interrupt on the one CPU we
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- * just elected
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+ int rxq_map = 0, txq_map = 0;
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+ int rxq;
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+
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+ for (rxq = 0; rxq < rxq_number; rxq++)
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+ if ((rxq % max_cpu) == cpu)
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+ rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
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+
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+ if (i == online_cpu_idx) {
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+ /* Map the default receive queue and transmit
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+ * queue to the elected CPU
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*/
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- smp_call_function_single(cpu, mvneta_percpu_enable,
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- pp, true);
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- else
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- /* Disable per-CPU interrupt on all the other CPU */
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- smp_call_function_single(cpu, mvneta_percpu_disable,
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- pp, true);
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+ rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
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+ txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
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+ }
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+ mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
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+
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+ /* Update the interrupt mask on each CPU according the
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+ * new mapping
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+ */
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+ smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
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+ pp, true);
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i++;
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+
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}
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};
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@@ -2802,12 +2867,22 @@ static int mvneta_percpu_notifier(struct
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mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
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napi_enable(&port->napi);
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+
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+ /* Enable per-CPU interrupts on the CPU that is
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+ * brought up.
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+ */
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+ smp_call_function_single(cpu, mvneta_percpu_enable,
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+ pp, true);
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+
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/* Enable per-CPU interrupt on the one CPU we care
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* about.
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*/
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mvneta_percpu_elect(pp);
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- /* Unmask all ethernet port interrupts */
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+ /* Unmask all ethernet port interrupts, as this
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+ * notifier is called for each CPU then the CPU to
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+ * Queue mapping is applied
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+ */
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mvreg_write(pp, MVNETA_INTR_NEW_MASK,
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MVNETA_RX_INTR_MASK(rxq_number) |
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MVNETA_TX_INTR_MASK(txq_number) |
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@@ -2858,7 +2933,7 @@ static int mvneta_percpu_notifier(struct
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static int mvneta_open(struct net_device *dev)
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{
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struct mvneta_port *pp = netdev_priv(dev);
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- int ret;
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+ int ret, cpu;
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pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
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pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
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@@ -2888,8 +2963,13 @@ static int mvneta_open(struct net_device
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*/
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mvneta_percpu_disable(pp);
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- /* Elect a CPU to handle our RX queue interrupt */
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- mvneta_percpu_elect(pp);
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+ /* Enable per-CPU interrupt on all the CPU to handle our RX
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+ * queue interrupts
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+ */
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+ for_each_online_cpu(cpu)
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+ smp_call_function_single(cpu, mvneta_percpu_enable,
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+ pp, true);
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+
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/* Register a CPU notifier to handle the case where our CPU
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* might be taken offline.
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