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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
156 lines
4.0 KiB
Diff
156 lines
4.0 KiB
Diff
From 125681433c8e526356947acf572fe8ca8ad32291 Mon Sep 17 00:00:00 2001
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From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
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Date: Sat, 30 Jan 2021 10:50:05 +0530
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Subject: [PATCH] remoteproc: qcom: Add PRNG proxy clock
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PRNG clock is needed by the secure PIL, support for the same
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is added in subsequent patches.
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Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
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---
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drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++--------
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1 file changed, 47 insertions(+), 18 deletions(-)
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--- a/drivers/remoteproc/qcom_q6v5_wcss.c
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+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
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@@ -91,19 +91,6 @@ enum {
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WCSS_QCS404,
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};
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-struct wcss_data {
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- const char *firmware_name;
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- unsigned int crash_reason_smem;
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- u32 version;
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- bool aon_reset_required;
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- bool wcss_q6_reset_required;
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- const char *ssr_name;
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- const char *sysmon_name;
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- int ssctl_id;
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- const struct rproc_ops *ops;
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- bool requires_force_stop;
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-};
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-
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struct q6v5_wcss {
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struct device *dev;
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@@ -128,6 +115,7 @@ struct q6v5_wcss {
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struct clk *qdsp6ss_xo_cbcr;
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struct clk *qdsp6ss_core_gfmux;
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struct clk *lcc_bcr_sleep;
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+ struct clk *prng_clk;
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struct regulator *cx_supply;
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struct qcom_sysmon *sysmon;
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@@ -151,6 +139,21 @@ struct q6v5_wcss {
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struct qcom_rproc_ssr ssr_subdev;
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};
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+struct wcss_data {
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+ int (*init_clock)(struct q6v5_wcss *wcss);
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+ int (*init_regulator)(struct q6v5_wcss *wcss);
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+ const char *firmware_name;
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+ unsigned int crash_reason_smem;
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+ u32 version;
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+ bool aon_reset_required;
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+ bool wcss_q6_reset_required;
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+ const char *ssr_name;
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+ const char *sysmon_name;
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+ int ssctl_id;
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+ const struct rproc_ops *ops;
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+ bool requires_force_stop;
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+};
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+
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static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
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{
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int ret;
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@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc
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struct q6v5_wcss *wcss = rproc->priv;
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int ret;
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+ ret = clk_prepare_enable(wcss->prng_clk);
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+ if (ret) {
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+ dev_err(wcss->dev, "prng clock enable failed\n");
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+ return ret;
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+ }
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+
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qcom_q6v5_prepare(&wcss->q6v5);
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/* Release Q6 and WCSS reset */
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@@ -733,6 +742,7 @@ static int q6v5_wcss_stop(struct rproc *
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return ret;
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}
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+ clk_disable_unprepare(wcss->prng_clk);
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qcom_q6v5_unprepare(&wcss->q6v5);
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return 0;
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@@ -900,7 +910,21 @@ static int q6v5_alloc_memory_region(stru
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return 0;
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}
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-static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
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+static int ipq8074_init_clock(struct q6v5_wcss *wcss)
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+{
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+ int ret;
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+
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+ wcss->prng_clk = devm_clk_get(wcss->dev, "prng");
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+ if (IS_ERR(wcss->prng_clk)) {
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+ ret = PTR_ERR(wcss->prng_clk);
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+ if (ret != -EPROBE_DEFER)
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+ dev_err(wcss->dev, "Failed to get prng clock\n");
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+ return ret;
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+ }
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+ return 0;
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+}
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+
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+static int qcs404_init_clock(struct q6v5_wcss *wcss)
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{
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int ret;
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@@ -990,7 +1014,7 @@ static int q6v5_wcss_init_clock(struct q
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return 0;
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}
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-static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
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+static int qcs404_init_regulator(struct q6v5_wcss *wcss)
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{
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wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
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if (IS_ERR(wcss->cx_supply))
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@@ -1034,12 +1058,14 @@ static int q6v5_wcss_probe(struct platfo
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if (ret)
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goto free_rproc;
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- if (wcss->version == WCSS_QCS404) {
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- ret = q6v5_wcss_init_clock(wcss);
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+ if (desc->init_clock) {
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+ ret = desc->init_clock(wcss);
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if (ret)
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goto free_rproc;
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+ }
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- ret = q6v5_wcss_init_regulator(wcss);
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+ if (desc->init_regulator) {
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+ ret = desc->init_regulator(wcss);
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if (ret)
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goto free_rproc;
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}
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@@ -1086,6 +1112,7 @@ static int q6v5_wcss_remove(struct platf
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}
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static const struct wcss_data wcss_ipq8074_res_init = {
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+ .init_clock = ipq8074_init_clock,
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.firmware_name = "IPQ8074/q6_fw.mdt",
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.crash_reason_smem = WCSS_CRASH_REASON,
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.aon_reset_required = true,
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@@ -1095,6 +1122,8 @@ static const struct wcss_data wcss_ipq80
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};
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static const struct wcss_data wcss_qcs404_res_init = {
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+ .init_clock = qcs404_init_clock,
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+ .init_regulator = qcs404_init_regulator,
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.crash_reason_smem = WCSS_CRASH_REASON,
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.firmware_name = "wcnss.mdt",
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.version = WCSS_QCS404,
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