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2e0b000e0e
Remove patches that were upstreamed, and backport features from later kernels. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
60 lines
1.9 KiB
Diff
60 lines
1.9 KiB
Diff
From 99942611816c117a01f16dbcab54908a49b378c3 Mon Sep 17 00:00:00 2001
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From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
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Date: Mon, 18 Dec 2023 12:05:39 +0100
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Subject: [PATCH 02/14] riscv: dts: allwinner: Update opp table to allow CPU
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frequency scaling
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Two OPPs are currently defined for the D1/D1s; one at 408MHz and
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another at 1.08GHz. Switching between these can be done with the
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"sun50i-cpufreq-nvmem" driver. This patch populates the opp table
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appropriately, inspired by
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https://github.com/Tina-Linux/linux-5.4/blob/master/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi
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The supply voltages are PWM-controlled, but support for that IP
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is still in the works. So stick to a target vdd-cpu supply of 0.9V,
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which seems to be the default on most D1 boards.
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Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
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---
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arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 18 +++++++++++++++---
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1 file changed, 15 insertions(+), 3 deletions(-)
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--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
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+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
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@@ -36,16 +36,22 @@
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};
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opp_table_cpu: opp-table-cpu {
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- compatible = "operating-points-v2";
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+ compatible = "allwinner,sun20i-d1-operating-points",
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+ "allwinner,sun50i-h6-operating-points";
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+ nvmem-cells = <&cpu_speed_grade>;
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+ nvmem-cell-names = "speed";
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+ opp-shared;
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opp-408000000 {
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <408000000>;
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- opp-microvolt = <900000 900000 1100000>;
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+ opp-microvolt-speed0 = <900000 900000 1100000>;
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};
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opp-1080000000 {
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1008000000>;
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- opp-microvolt = <900000 900000 1100000>;
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+ opp-microvolt-speed0 = <900000 900000 1100000>;
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};
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};
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@@ -112,3 +118,9 @@
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<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
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};
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};
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+
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+&sid {
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+ cpu_speed_grade: cpu-speed-grade@0 {
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+ reg = <0x00 0x2>;
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+ };
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+};
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